• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.16-24
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• 2009

Independent-gate-mode double-gate(IGM-DG) MOSFET overcomes the limitation of 3-terminal device structure, and enables to operate with different voltages for front-gate and back-gate. Therefore, circuit designs becomes not only simple, but also area-efficient due to the controllability of the 4th terminal provided by IGM-DG MOSFETs. In this paper, an RF receiver utilizing IGM-DG MOSFETs is presented and also, the circuit performance is verified by the HSPICE simulations. Besides, the circuit analysis and optimization are performed for various IGM-DG characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.498-501
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator. DG MOSFET have the main gate length of nm and the side gate length of 70nm. Then, we have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nino scale.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.15-22
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• 2008

The bulk-planer MOSFET has a scaling limitation due to the short channel effect (SCE). The Double-Gate MOSFET (DG-MOSFET) is a next generation device for nanoscale with excellent control of SCE. The quantum effect in lateral direction is important for subthreshold characteristics when the effective channel length of DG-MOSFET is less than 10nm, Also, ballistic transport is setting important. This study shows modeling and design issues of nanoscale DG-MOSFET considering the 2D quantum effect and ballistic transport. We have optimized device characteristics of DG-MOSFET using a proper value of $t_{si}$ underlap and lateral doping gradient.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.500-510
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• 2013

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1074-1078
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator U .WOSFET have the main gate length of %m and the side gate length of 70nm. Then, u'e have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nano scale.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.263-268
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• 2003

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.27-31
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• 2004

Models and simulations of gate tunneling current for thinoxide MOSFETs and Double-Gate SOIs are discussed. A guideline in design of leaky MOS capacitors is proposed and resonant gate tunneling current in DG SOI simulated based on quantum-mechanicalmodels. Gate tunneling current in fully-depleted, double-gate SOI MOSFETs is characterized based on quantum-mechanical principles. The simulated $I_G-V_G$ of double-gate SOI has negative differential resistance like that of the resonant tunnel diodes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.13-22
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• 2010

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET overcomes the limitation of bulk-MOSFET's channel controllability and enables to control the front and back-gate voltages independently. Therefore, circuit designs utilizing the IGM-DG MOSFETs provide the advantage of setting 4-terminal freely, hence achieving not only the performance improvement but also the larger scale integration. This paper presents a 15Gb/s optical receiver with a 1.0V power supply voltage, which consists of a transimpedance amplifier (TIA), a feedforward limiting amplifier (LA), and an output buffer. HSPICE simulations were conducted to confirm the circuit performance, and also to verify the circuit stability issues which may occur from the variations of process and supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.777-779
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• 2003

In this paper, we have investigated Characteristics of C-V for Double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated characteristics of C-V and main gate voltage is changed from -5V to ＋5V. Also we have investigated characteristics of C-V for DG MOSFET when the side gate length is changed from 40nm to 90nm. As the side gate length is reduced, the transconductance is increased and the capacitance is reduced. When the side gate voltage is 3V, we know that C-V curves are bending at near the main gate voltage of 1.8V. We have simulated using ISE-TCAD tool for characteristics analysis of device.