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Woo Yong Choi, Byung Yong Choi, Dong Soo Woo, Young Jin Choi, Jong Duk Le and Byung Gook Park, 'Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain', Jpn. J. Appl. Phys., Vol. 41, Part 1, No. 4B, pp. 2345-2347, 2002
DOI
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Byung Yong Choi, Suk Kang Sung, Byung Gook Park and Jong Duk Lee, '70nm NMOSFET Fabrication with 12nm n+-p Junctions Using As2+ Low Engergy Implantations', Jpn. J. Appl. Phys., Vol. 40, Part1, No. 4B, pp. 2607-2610, 2001
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3 |
X. Zhou, K. Y. Lim, W. Qian, 'Threshold voltage definition and extration for deep-submicron MOSFETs', Solid-State Electronics, Vol. 45, pp.507-510, 2001
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Young Jin Choi, Byoung Yong Choi, Kyung Rok Kim, Jong Duk Lee and Byung Gook Park, 'A New 50-nm nMOSFET With Side-Gates for Virtual Source-Drain Extensions', IEEE Trans, Electron Dev., Vol. 49, No. 10, pp. 1833-1835, 2002
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ScienceOn
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김영동, 김재홍, 정학기, '나노구조 MOSFET의 문턱전압 변화를 최소화하기 위한 스케일링 이론', 한국해양정보통신학회 추계종합학술대회논문집, Vol. 6, No. 2, pp. 494-497, 2002
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