• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.115-121
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• 2013

We fabricated thin film transistors (TFTs) using TiInZnO(TiIZO) thin films as active channel layer. The thin films of TiIZO were deposited at room temperature by RF-magnetron co-sputtering system from InZnO(IZO) and Ti targets. We examined the effects of titanium addition by X-ray diffraction, X-ray photoelectron spectroscopy and the electrical characteristics of the TFTs. The TiIZO TFTs were investigated according to the radio-frequency power applied to the Ti target. We found that the transistor on-off currents were greatly influenced by the composition of titanium addition, which suppressed the formation of oxygen vacancies, because of the stronger oxidation tendency of Ti relative to that of Zn or In. A optimized TiIZO TFT with rf power 40W of Ti target showed good performance with an on/off current ratio greater than $10^5$, a field-effect mobility of 2.09 [$cm^2/V{\cdot}s$], a threshold voltage of 2.2 [V] and a subthreshold swing of 0.492 [V/dec.].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.1-7
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• 2006

3-dimensional(3-D) simulations of ideal double-gate bulk FinFET were performed extensively and the electrical characteristics. were analyzed. In 3-D device simulation, we changed gate length($L_g$), height($H_g$), and channel doping concentration($N_b$) to see the behaviors of the threshold voltage($V_{th}$), DIBL(drain induced barrier lowering), and SS(subthreshold swing) with source/drain junction depth($X_{jSDE}$). When the $H_g$ is changed from 30 nm to 45nm, the variation gives a little change in $V_{th}$(less than 20 mV). The DIBL and SS were degraded rapidly as the $X_{jSDE}$ is deeper than $H_g$ at low fin body doping($1{\times}10^{16}cm^{-3}{\sim}1{\times}10^{17}cm^{-3}$). By adopting local doping at ${\sim}10nm$ under the $H_g$, the degradation could be suppressed significantly. The local doping also alleviated $V_{th}$ lowering by the shallower $X_{jSDE}\;than\;H_g$ at low fin body doping.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.575-580
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• 2015

Asymmetric double gate(DG) MOSFET is a novel transistor to be able to reduce the short channel effects. This paper has analyzed a off current for conduction path of asymmetric DGMOSFET. The conduction path is a average distance from top gate the movement of carrier in channel happens, and a factor to change for oxide thickness of asymmetric DGMOSFET to be able to fabricate differently top and bottom gate oxide thickness, and influenced on off current for top gate voltage. As the conduction path is obtained and off current is calculated for top gate voltage, it is analyzed how conduction path influences on off current with parameters of oxide thickness and channel length. The analytical potential distribution of series form is derived from Poisson's equation to obtain off current. As a result, off current is greatly changed for conduction path, and we know threshold voltage and subthreshold swing are changed for this reasons.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1199-1202
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• 2008

High mobility bottom gate thin film transistors (TFTs) with an amorphous gallium tin zinc oxide (a-GSZO) channel layer have been produced by rf magnetron cosputtering using a gallium zinc oxide (GZO) and tin (Sn) targets. The effect of the post annealing temperatures ($200^{\circ}C$, $250^{\circ}C$ and $300^{\circ}C$) was evaluated and compared with two series of TFTs produced at room temperature and $150^{\circ}C$ during the channel deposition. From the results it was observed that the effect of pos annealing is crucial for both series of TFTs either for stability as well as for improving the electrical characteristics. The a-GSZO TFTs operate in the enhancement mode (n-type), present a high saturation mobility of $24.6\;cm^2/Vs$, a subthreshold gate swing voltage of 0.38 V/decade, a turn-on voltage of -0.5 V, a threshold voltage of 4.6 V and an $I_{ON}/I_{OFF}$ ratio of $8{\times}10^7$, satisfying all the requirements to be used in active-matrix backplane.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.330-332
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• 2009

Highly stable bottom gate thin film transistors(TFTs) with a zinc indium tin oxide(Zn-In-Sn-O:ZITO) channel layer have been fabricated by rf-magnetron co-sputtering using a indium tin oxide(ITO:90/10), a tin oxide and a zinc oxide targets. The ZITO TFT (W/L=$40{\mu}m/20{\mu}m$) has a mobility of 24.6 $cm^2$/V.s, a subthreshold swing of 0.12V/dec., a turn-on voltage of -0.4V and an on/off ratio of >$10^9$. When gate field of $1.8{\times}10^5$ V/cm was applied with source-drain current of $3{\mu}A$ at $60^{\circ}C$, the threshold voltage shift was ~0.18 V after 135 hours. We fabricated AM-OLED driven by highly stable bottom gate Zn-In-Sn-O TFT array.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.458-462
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• 2011

Soution-processed ZrInZnO (ZIZO) thin-film transistors (TFTs) with varying Zr content were fabricated. The ZIZO TFT (Zr=20 at. %/Zn) has an optimal performance with the saturation field effect mobility of 0.77 $cm^2/Vs$, the threshold voltage (Vth) of 2.1 V, the on/off ratio of $4.95{\times}10^6$, and subthreshold swing (S.S) of 0.73 V/decade. Using this optimized ZIZO TFT, the positive and negative gate bias stress according to annealing temperature was also investigated. While the Vth shifts dramatically after 1,000 s of both gate bias stresses, variations in the S.S are negligible. It suggests that electrons or holes are tem porarily trapped in the gate insulator, the semiconductor, or the interface between both layers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.666-672
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• 2014

We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal $SiO_2$, a plasma-enhanced chemical vapor deposition (PECVD) $SiO_x$, a $150^{\circ}C$-deposited PEVCD $SiO_x$, and a $300^{\circ}C$-deposited PECVD $SiO_x$. Among the devices, the one with the $150^{\circ}C$-deposited PEVCD $SiO_x$ exhibits the best electrical performance including a high field-effect mobility ($=4.86cm^2/Vs$), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localized-trap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2324-2332
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• 2017

This paper presents the electrical performances of novel AlGaSb/InGaAs heterojunction-based vertical-tunneling field-effect transistor (VTFET). The device performance was investigated in views of the on-state current ($I_{on}$), drain-induced barrier thinning (DIBT), and subthreshold swing (SS) as the gate length ($L_G$) was scaled down. The proposed TFET with a $L_G$ of 5 nm operated with an $I_{on}$ of $1.3mA/{\mu}m$, a DIBT of 40 mV/V, and an SS of 23 mV/dec at a drain voltage ($V_{DS}$) of 0.23 V. The proposed TFET provided approximately 25 times lower DIBT and 12 times smaller SS compared with the conventional $L_G$ of 5 nm TFET. The AlGaSb/InGaAs VTFET showed extremely high scalability and strong immunity against short-channel effects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.