1 |
G. Deng anf C. Chen, "Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors", IEEE Trans. on VLSI systems, vol.21, no.9, pp.1573-1582, 2013.
DOI
ScienceOn
|
2 |
J.P.Duarte, S.J.Choi, D.I.Moon and Y.K.Choi, "A nonpiecewise model for long-channel junctionless cylindrical nanowire FETs," IEEE Electron Device Letters, vol.33, no.2, pp.155-157, 2012.
DOI
ScienceOn
|
3 |
M.C.Cheng, J.A.Smith, W.Jia and R.Coleman, "An Effective Thermal Model for FinFET Structure," IEEE Trans. Electron Devices, vol. 61, no.1, pp.202-206, 2014.
DOI
ScienceOn
|
4 |
Z.Ding, G.Hu, J.Gu, R.Liu, L.Wang and T.Tang,"An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs," Microelectronics J., vol.42, pp.515-519, 2011.
DOI
ScienceOn
|
5 |
H.K.Jung and D.S.Cheong,"Analysis for Relation of Oxide Thickness and Subthreshold Swing of Asymmetric Double Gate MOSFET," Conference on Information and Communication Eng., vol.17, no.2, pp.698-701, 2013.
|
6 |
H.K.Jung and S.Dimitrijev, "Analysis of Subthreshold Carrier Transport for Ultimate DGMOSFET," IEEE Trans. Electron Devices, vol. 53, no.4, pp.685-691, 2006.
DOI
|
7 |
TCAD Manual, Part.4: INSPEC, ISE Integrated Systems Engineering AG, Zurich, Switzerland, 2001, p.56. ver.7.5.
|