• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1069-1072
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• 2003

Germane-sillicide phase formation on S $i_{0.25}$G $e_{0.75}$ with Ni 100$\square$, Co 10$\square$/Ni 100$\square$ and Ni 50$\square$/Co 10$\square$/Ni 50$\square$ layer was studied by sheet resistance and Field Emission Scanning Electron Microscopy(FESEM). Thermal stability of nickel germane-silicide is found to be improved by sputtering Ni/Co/Ni on the SiGe. After annealing at 600, 650, $700^{\circ}C$, 30min., the nickel germane-silicide formed by Ni 50$\square$/Co 10$\square$/Ni 50$\square$ layer achieved a sheet resistance less than 17ohms/sq.(almost the same to the value before furnace annealing for 30min.) , while the process of the other two ways result in high sheet resistance and even sheet resistance fail due to Ge segregation.ion.

• 한국세라믹학회지
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• 제27권5호
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• pp.645-651
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• 1990

Effects of excess Si on the properities of the oxide of CVD tungsten silicide were investigated by comparing the characteristics of the two kinds of thermal oxide for CVD-WSi2.7 and WSi3.1 films on the polycrystalline Si film each other. It is reveraled from AES analysis that Si in the surface region of the silicide film is consumed to make composition and resistivity of the silicide film very nonuniform for the case of the oxidation of WSi3.1, while the underlayer polycrystalline Si was consumed for the case of the oxidation of WSi2.7.

• 대한전자공학회논문지SD
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• 제40권11호
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• pp.1-8
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• 2003

본 논문에서는 소스/드레인 및 게이트의 불순물에 따른 실리사이드의 의존성을 면저항과 단면 특성 등의 분석을 통하여 연구하였다. 급속 열처리 후에는 As, P, BF₂, B/sub 11/ 등과 같은 불순물에 대한 먼저항의 차이가 거의 나지 않았다. 하지만 실리사이드 형성 후히 고온 열처리시에 그 특성이 매우 크게 변화하였다. BF₂를 주입한 시편에서의 특성이 가장 좋게 나타난 반면, As를 주입한 실리사이드의 특성이 가장 열화되었다. BF₂를 주입한 시편에서의 실리사이드 특성 향상은 flourine에 의한 니켈의 확산 방지 때문인 것으로 여겨진다. 그러므로 실리사이드의 성능 향상을 위해 Ni의 확산을 방지시키는 것이 매우 필요하다.

• 한국재료학회지
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• 제16권9호
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.

• 한국재료학회지
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• 제17권2호
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• 마이크로전자및패키징학회지
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• 제12권2호
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• pp.149-154
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• 2005

궁극적으로 게이트를 저저항 복합 실리사이드로 대체하는 가능성을 확인하기 위해 70 nm 두께의 폴리실리콘 위에 각 20nm의 Ni, Co를 열증착기로 적층순서를 달리하여 poly/Ni/Co, poly/Co/Ni구조를 만들었다. 쾌속열처리기를 이용하여 실리사이드화 열처리를 40초간 $700{\~}1100^{\circ}C$ 범위에서 실시하였다. 복합 실리사이드의 온도별 전기저항변화, 두께변화, 표면조도변화를 각각 사점전기저항측정기와 광발산주사전자현미경, 주사탐침현미경으로 확인하였다. 적층순서와 관계없이 폴리실리콘으로부터 제조된 복합실리사이드는 $800^{\circ}C$ 이상부터 급격한 고저항을 보이고, 두께도 급격히 얇아졌다. 두께의 감소는 기존의 단결정에서는 없던 현상으로 폴리실리콘의 두께가 한정된 경우 금속성분의 inversion 현상이 커서 폴리실리콘이 오히려 실리사이드 상부에 위치하여 제거되기 때문이라고 생각되었고 $1000^{\circ}C$ 이상에서는 실리사이드가 형성되지 못하였다. 이러한 결과는 나노급 두께의 게이트를 저저항 실리사이드로 만 들기 위해서는 inversion과 두께감소를 고려하여야 함을 의미하였다.

• 마이크로전자및패키징학회지
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• 제13권1호통권38호
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• pp.1-5
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• 2006

반도체 메모리 소자의 스피드 향상을 위해 저저항 배선층을 채용하는 방안으로 70 nm-두께의 아몰퍼스실리콘과 폴리실리콘 기판부에 $TiSi_2$ 타켓으로 각각 80 nm 두께의 TiSix 복합실리콘을 스퍼터링으로 증착한 후 RTA $800^{\circ}C$-20sec 조건으로 실리사이드화 처리하고 사진식각법으로 선폭 $0.5{\mu}m$의 배선층을 만들었다. 배선층에 대해 다시 각각 $750^{\circ}C-3hr,\;850^{\circ}C-3hr$의 부가적인 안정화 열처리를 실시하였으며, 이때의 면저항의 변화는 four-point probe로 실리사이드층의 미세구조와 수직단면 두께 변화를 주사전자현미경과 투과전자현미경으로 관찰하였다. 아몰퍼스실리콘 기판인 경우 후속열처리에 따른 결정화 진행과 함께 급격한 면저항의 증가가 확인되었고, 이 원인은 결정화 과정에서 실리콘과 복합티타늄실리사이드 층과의 상호확산으로 표면 공공(void)을 형성한 것으로 미세구조 관찰에서 확인되었다. 따라서 복합티타늄실리사이드의 하지층의 종류와 열처리 조건을 바꾸어 저저항 또는 고저항 실리사이드를 조절하여 제작하는 것이 가능하여 복합 $TiSi_2$를 저저항 배선층 재료로 채용할 수 있음을 확인하였다.

• Transactions on Electrical and Electronic Materials
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• 제9권2호
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• pp.47-51
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• 2008

In this paper, thermal stability of Nickel silicide formed on p-type silicon wafer using Ni-V alloy film was studied. As compared with pure Ni, Ni-V shows better thermal stability. The addition of Vanadium suppresses the phase transition of NiSi to $NiSi_2$ effectively. Ni-V single structure shows the best thermal stability compared with the other Ni-silicide using TiN and Co/TiN capping layers. To enhance the thermal stability up to $650^{\circ}C$ and find out the optimal thickness of Ni silicide, different thickness of Ni-V was also investigated in this work.

• 한국재료학회지
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• 제18권1호
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• pp.5-11
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• 2008

Thermally evaporated 10 nm-Ni/1 nm-Au/(30 nm-poly)Si structures were fabricated in order to investigate the thermal stability of Au-inserted nickel silicide. The silicide samples underwent rapid thermal annealing at $300{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance was measured using a four-point probe. A scanning electron microscope and a transmission electron microscope were used to determine the cross-sectional structure and surface image. High-resolution X-ray diffraction and a scanning probe microscope were employed for the phase and surface roughness. According to sheet resistance and XRD analyses, nickel silicide with Au had no effect on widening the NiSi stabilization temperature region. Au-inserted nickel silicide on a single crystal silicon substrate showed nano-dots due to the preferred growth and a self-arranged agglomerate nano phase due to agglomeration. It was possible to tune the characteristic size of the agglomerate phase with silicidation temperatures. The nano-thick Au-insertion was shown to lead to self-arranged microstructures of nickel silicide.