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Property of Composite Silicide from Nickel Cobalt Alloy

니켈 코발트 합금조성에 따른 복합실리사이드의 물성 연구

  • Kim, Sang-Yeob (Department of Materials Science and Engineering, The University of Seoul) ;
  • Song, Oh-Sung (Department of Materials Science and Engineering, The University of Seoul)
  • Published : 2007.02.27

Abstract

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

Keywords

References

  1. J. Y. Dai, Z. R. Guo, S. F. Tee, C. L. Tay, E. Er and S. Redkar, Appl. Phys. Lett., 78, 3091 (2001) https://doi.org/10.1063/1.1372621
  2. J. Prokop, C. E. Zybill and S. Veprek, Thin Solid Films, 359, 39 (2000) https://doi.org/10.1016/S0040-6090(99)00654-9
  3. C. Detavemier, R. L. Van Meirhaeghe and F. Cardon, J. Appl. Phys., 88, 133 (2000) https://doi.org/10.1063/1.373633
  4. The International Technology RoadMap For Semiconductor, Front End Process, p. 25, SIA, 2003 Edition (2003)
  5. J. Chen, J. P. Colinge, D. Flandre, R. Gillon, J. P. Raskin and D. Vanhoenacker, J. Electrochem. Soc., 7, 144 (1997) https://doi.org/10.1149/1.1837833
  6. J. J. Sun, J. Y. Tsai and C. M. Osburn, IEEE Trans. on Electron Devices, 45, 1946 (1998) https://doi.org/10.1109/16.678583
  7. Semiconductor Industry Association(SIA), the international technology road map for semiconductors, Front End Process, pp.23 (2004)
  8. E. J. Jung, S. W. Jung, H. S. Kim and J. H. Yun, Microelectronic Eng., 82, 449 (2005) https://doi.org/10.1016/j.mee.2005.07.041
  9. B. A. Julies, D. Knoesen, R. Pretorius and D. Adams, Thin Solid Films, 347, 201 (1999) https://doi.org/10.1016/S0040-6090(99)00004-8
  10. O. S. Song, S. H. Cheong and D. J. Kim, Kor. J. Mate. Res., 14(12), 846 (2004) https://doi.org/10.3740/MRSK.2004.14.12.846
  11. E. J. Jung, S. W. Jung, H. S. Kim and J. H. Yun, Microelectronic Eng., 82, 449 (2005) https://doi.org/10.1016/j.mee.2005.07.041
  12. E. G. Colgan, J. P. Gambino and Q. Z. Hong, Mater. Sci. Eng., 16, 43 (1996) https://doi.org/10.1016/0927-796X(95)00186-7
  13. J. H. Ku, C.-J. Choi, S. Song, S. Choi, K. Fujihara, H.-K. Kang and S.-I. Lee, VLSI Tech. Symp., 114 (2000) https://doi.org/10.1109/VLSIT.2000.852791