Browse > Article
http://dx.doi.org/10.5573/JSTS.2007.7.2.082

Influences of Trap States at Metal/Semiconductor Interface on Metallic Source/Drain Schottky-Barrier MOSFET  

Cho, Won-Ju (Department of Electronic Materials Engineering, Kwangwoon University)
Publication Information
Abstract
The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.
Keywords
metallic junction; Schottky barrier MOSFET; interface trap; forming gas annealing;
Citations & Related Records
연도 인용수 순위
  • Reference
1 B.-Y. Tsui and C.-P. Lin, 'A novel 25-nm modified Schottky-barrier FinFET with high performance,' IEEE Electron Device Lett., vol. 25, no. 6, pp. 430-432, Jun. 2004   DOI   ScienceOn
2 R. T. Tung, 'Electron transport at metalsemiconductor interfaces: general theory,' Phys. Rev. B, Condens. Matter, vol. 45, pp. 13509-13523 (1992)   DOI   ScienceOn
3 R. B. Darling, 'Current-voltage characteristics of Schottky barrier diodes with dynamic interfacial defect state occupancy,' IEEE Trans. Electron. Devices, vol. 43, no. 7, pp. 1153-1160 (1996)   DOI   ScienceOn
4 C. John G. Shaw and M. Hack, 'An analytical model for calculating trapped charge in amorphous silicon', Journal of Appl. Phys., 64 (9), pp.4562-4566 (1988)   DOI
5 ATLAS User's Manual, SILVACO, Vol. 2, pp. 13.1-13.5 (2002)
6 S. Matsumoto, M. Nishisaka, and T. Asano, 'CMOS application of Schottky S/D SOI MOSFET with shallow doped extension,' Jpn. J. Appl. Phys., vol. 43, no. 4B, pp. 2170-2175, 2004   DOI
7 E. Dubois and G. Larrieu, 'Measurement of low Schottky barrier heights applied to S/D metaloxide-semiconductor field effect transistors,' J. Appl. Phys., vol. 96, no. 1, pp. 729-737, Jul. 2004   DOI   ScienceOn
8 A. M. Kemp, M. Meunier and C. G. Tannous, 'Simulations of the amorphous silicon static induced transistor', Solid-State Elect., Vol. 32, No. 2, pp.149-157 (1989)   DOI   ScienceOn
9 B. M. Hack and J. G. Shaw, 'Numerical simulations of amorphous and polycrystalline silicon thin-film transistors', Extended Abstracts 22nd International conference on Solid-State Device and Materials, pp.999-1002 (1990)
10 J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, 'Complementary silicide S/D thin-body MOSFETs for the 20 nm gate length regime,' IEDM Tech. Dig., 2000, pp. 57-60
11 'Front end processes,' in International Technology Roadmap for Semiconductors 2003 Edition. Austin, TX: Semiconductor Industry Assoc., 2003