• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.37-45
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• 1998

In this paper, we report the first three-dimensional simulation result of the transient enhanced diffusion(TED) of dopants in the ion-implanted silicon by employing our 3D semiconductor process simulator, INPROS system. In order to simulate three-dimensional TED redistribution of dopants in silicon, the dopant distributions after the ion implantation was calculated by Monte Carlo(MC) method, followed by finite element(FE) numerical solver for thermal annealing. Excellent agreement between the simulated 3D profile and the SIMS data has been obtained for ion-implanted arsenic and phosphorus after annealing the boron marker layer at 75$0^{\circ}C$ for 2 hours. Our three-dimensional TED simulation could successfully explain the reverse short channel effect(RSCE) by taking the 3D point defect distribution into account. A coupled TED simulation and device simulation allows reverse short channel effect on threshold to be accurately predicted.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.278-286
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• 2011

In this paper, we present a compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths ($L_g$) and radii (R). Schr$\ddot{o}$dinger's equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.120-131
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• 2007

A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

• ETRI Journal
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• v.39 no.2
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• pp.284-291
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• 2017

Drain-induced barrier lowering (DIBL) is one of the main parameters employed to indicate the short-channel effect for nano metal-oxide semiconductor field-effect transistors (MOSFETs). We propose a new physical model of the DIBL effect under two-dimensional approximations based on the energy-conservation equation for channel electrons in FETs, which is different from the former field-penetration model. The DIBL is caused by lowering of the effective potential barrier height seen by the channel electrons because a lateral channel electric field results in an increase in the average kinetic energy of the channel electrons. The channel length, temperature, and doping concentration-dependent DIBL effects predicted by the proposed physical model agree well with the experimental data and simulation results reported in Nature and other journals.

• Journal of Sensor Science and Technology
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• v.29 no.5
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• pp.324-327
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• 2020

The impact of output conductance (g_o) on the short-circuit current-gain cut-off frequency (f_T) in In_0.8Ga_0.2As high-electron-mobility transistors (HEMTs) on an InP substrate was investigated. An attempted was made to extract the values of f_T in a simplified small-signal model (SSM) of the HEMTs, derive an analytical formula for f_T in terms of the extrinsic model parameters of the simplified SSM, which are related to the intrinsic model parameters of a general SSM, and verify its validity for devices with L_g from 260 to 25 nm. In long-channel devices, the effect of the intrinsic output conductance (g_oi) on f_T was negligible. This was because, from the simplified SSM perspective, three model parameters, such as g_{m_ext}, C_{gs_ext} and C_{gd_ext}, were weakly dependent on g_oi. However, in short-channel devices, g_oi was found to play a significant role in degrading f_T as L_g was scaled down. The increase in g_oi in short-channel devices caused a considerable reduction in g_{m_ext} and an overall increase in the total extrinsic gate capacitance, yielding a decrease in f_T with g_oi. Finally, the results were used to infer how f_T is influenced by g_oi in HEMTs, emphasizing that improving electrostatic integrity is also critical importance to benefit fully from scaling down L_g.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.25-32
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• 2005

In this paper, it is attempted to provide a unified explanation for typical short channel GaAs MESFET’s and SOI-structured Si JFET's behaviors such as: i) drain voltage-induced threshold voltage roll-off, ii) finite output ac resistance beyond the saturation, and iii) weak dependence of the drain saturation current on the channel length. Replacing the conventional GCA with a new assumption that is suggested in order to include the longitudinal field variation, and taking into account the channel current continuity and the field-dependent mobility, we can derive the two-dimensional potential in both depletion region and undepleted conducting channel. Obtained expressions for the threshold voltage and the drain current will be considerably accurate over the entire operating region. Moreover, in comparison with the conventional channel length shortening models, our model seems to be more reasonable in explaining the Early effect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.17-23
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• 2010

In this paper, a new analytical model for deriving the threshold voltage of a short-channel bulk-type MOSFET is suggested. Using the Fourier coefficient method, the Laplace equation in the oxide region and the Poisson equation in the depleted silicon region have been solved two-dimensionally. Making use of them, the minimum surface potential is derived to describe the threshold voltage. Simulation results show good agreement with the dependencies of the threshold voltage on the various device parameters and applied bias voltages.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.5
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• pp.992-997
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• 2016

This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.130-133
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• 2010

This paper presents a study of the influence of variation of counter doping thickness on short channel effect in symmetric double-gate (DG) nano MOSFETs. Short channel effects are estimated from the computed values of current-voltage (I-V) characteristics. Two dimensional Quantum transport equations and Poisson equations are used to compute DG MOSFET characteristics. We found that the transconductance ($g_m$) and the drain conductance ($g_d$) increase with an increase in p-type counter-doping thickness ($T_c$). Very high value of transconductance ($g_m=38\;mS/{\mu}m$) is observed at 2.2 nm channel thickness. We have established that the threshold voltage of DG MOSFETs can be tuned by selecting the thickness of counter-doping in such device.