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Impact of Energy Relaxation of Channel Electrons on Drain-Induced Barrier Lowering in Nano-Scale Si-Based MOSFETs

  • Mao, Ling-Feng (School of Computer & Communication Engineering, University of Science & Technology Beijing)
  • Received : 2016.10.19
  • Accepted : 2017.02.02
  • Published : 2017.04.01
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Abstract

Drain-induced barrier lowering (DIBL) is one of the main parameters employed to indicate the short-channel effect for nano metal-oxide semiconductor field-effect transistors (MOSFETs). We propose a new physical model of the DIBL effect under two-dimensional approximations based on the energy-conservation equation for channel electrons in FETs, which is different from the former field-penetration model. The DIBL is caused by lowering of the effective potential barrier height seen by the channel electrons because a lateral channel electric field results in an increase in the average kinetic energy of the channel electrons. The channel length, temperature, and doping concentration-dependent DIBL effects predicted by the proposed physical model agree well with the experimental data and simulation results reported in Nature and other journals.

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References

  1. S.Y. Wu et al, "A 16 nm FinFET CMOS Technology for Mobile SoC and Computing Applications," IEEE Int. IEDM, Washington, DC, USA, Dec. 9-11, 2013, pp. 9.1.1-9.1.4.
  2. S. Bangsaruntip et al., "Density Scaling with Gate-All-Around Silicon Nanowire MOSFETs for the 10 nm Node and Beyond," IEEE Int. IEDM, Washington, DC, USA, Dec. 9-11, 2013, pp. 20.2.1-20.2.4.
  3. J.H. Huang et al., "A Physical Model for MOSFET Output Resistance," IEDM Tech. Dig., San Francisco, CA, USA, Dec. 13-16, 1992, pp. 569-572.
  4. M.J. Deen and Z.X. Yan, "DIBL in Short-Channel NMOS Devices at 77 K," IEEE Trans. Electron. Devices, vol. 39, no. 4, Apr. 1992, pp. 908-915. https://doi.org/10.1109/16.127482
  5. I. Ferain, C.A. Colinge, and J.P. Colinge, "Multigate Transistors as the Future of Classical Metal-Oxide-Semiconductor Field-Effect Transistors," Nature, vol. 479, no. 7373, Nov. 2011, pp. 310-316. https://doi.org/10.1038/nature10676
  6. S. Narasimha et al., "22 nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL," IEEE Int. IEDM Tech. Dig., San Francisco, CA, USA, Dec. 10-13, 2012, pp. 3.3.1-3.3.4.
  7. L.F. Mao, H. Ning, and J.Y. Wang, "The Current Collapse in AlGaN/GaN High-Electron Mobility Transistors Can Originate from the Energy Relaxation of Channel Electrons," PloS one, vol. 10, no. 6, June 2016, pp. 1-9.
  8. L.F. Mao et al., "Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors," Sci. Rep., vol. 5, Dec. 2015, pp. 1-11.
  9. L.F. Mao et al., "Physical Modeling of Activation Energy in Organic Semiconductor Devices Based on Energy and Momentum Conservations," Sci. Rep., vol. 6, Apr. 2016, pp. 1-12. https://doi.org/10.1038/s41598-016-0001-8
  10. V.T. Dolgopolov et al., "Energy Relaxation Time in a Two-Dimensional Electron Gas at a (001) Surface of Silicon," J. Experimental Theoretical Phy., vol. 62, no. 6, Dec. 1985, pp. 1219-1224.
  11. N. Balkan, Hot Electrons in Semiconductors: Physics and Devices, Oxford, UK: Oxford University Press, 1998, p. 385.
  12. C. Canali et al., "Electron and Hole Drift Velocity Measurements in Silicon and Their Empirical Relation to Electric Field and Temperature," IEEE Trans. Electron. Devices, vol. 22, no. 11, Nov. 1975, pp. 1045-1047. https://doi.org/10.1109/T-ED.1975.18267
  13. C.G. Sodini, P.K. Ko, and J.L. Moll, "The Effect of High Fields on MOS Device and Circuit Performance," IEEE Trans. Electron. Devices, vol. 31, no. 10, Oct. 1984, pp. 1386-1393. https://doi.org/10.1109/T-ED.1984.21721
  14. S.M. Sze and K.K. Ng, Physics of Semiconductor Devices, 3rd ed. Hoboken, NJ, USA: Wiley, 1996.
  15. A. Ruangphanit et al., "Substrate Bias Effects on Drain Induced Barrier Lowering (DIBL) in Short Channel NMOS FETs," Australian J. Basic Appl. Sci., vol. 3, no. 3, July 2009, pp. 1640-1644.
  16. A. Ruangphanit, M. Rangson, and V. Poyai, "The Parameters Mismatch Model of Threshold Voltage for the Narrow and Short Channel MOSFET," J. Appl. Sci. Res., vol. 3, no. 1, Jan. 2006, pp. 13-16.
  17. K.K. Young, "Short-Channel Effect in Fully Depleted SOI MOSFETs," IEEE Trans. Electron. Devices, vol. 36, no. 2, Feb. 1989, pp. 399-402. https://doi.org/10.1109/16.19942
  18. S. Lee et al., "SPICE-Compatible New Silicon Nanowire Field-Effect Transistors (SNWFETs) Model," IEEE Trans. Nanotechnol., vol. 8, no. 5, Oct. 2009, pp. 643-649. https://doi.org/10.1109/TNANO.2009.2019724
  19. R. Muanghlua, N. Vittayakorn, and A. Ruangphanit, "Channel Engineering for Submicron N-Channel MOSFET Based on TCAD Simulation," Australian J. Basic Appl. Sci., vol. 2, no. 3, Jan. 2008, pp. 406-411.
  20. K. Aoki, Nonlinear Dynamics and Chaos in Semiconductors, Boca Raton, FL, USA: CRC Press, 2000, p. 38.
  21. A.J. Sabbah and D.M. Riffe, "Femtosecond Pump-Probe Reflectivity Study of Silicon Carrier Dynamics," Phys. Rev. B, vol. 66, no. 16, Oct. 2002, p. 165217. https://doi.org/10.1103/PhysRevB.66.165217
  22. H. Batwani, M. Gaur, and M.J. Kumar, "Analytical Drain Current Model for Nanoscale Strained-Si/SiGe MOSFETs," Int. J. Comput. Math. Electr. Electron. Eng., vol. 28, no. 2, Mar. 2009, pp. 353-371. https://doi.org/10.1108/03321640910929263
  23. C. Jacoboni et al., "A Review of Some Charge Transport Properties of Silicon," Solid-State Electron., vol. 20, no. 2, Feb. 1977, pp. 77-89. https://doi.org/10.1016/0038-1101(77)90054-5
  24. M. Singh and A.K. Rana, "Study of Short Channel Effects on FDSOI MOSFET in Nano Regime-TCAD Simulation," ITSI TEEE, vol. 1, no. 6, Dec. 2013, pp. 27-30.
  25. S.C. Brugger and A. Schenk, "First-Principle Computation of Relaxation Times in Semiconductors for Low and High Electric Fields," Int. Conf. Simulation Semicond. Process. Devices, Tokyo, Japan, Sept. 1-3, 2005, pp. 151-154.
  26. K. Chain et al., "A MOSFET Electron Mobility Model of Wide Temperature Range (77-400 K) for IC Simulation," Semicond. Sci. Technol., vol. 12, no. 4, Apr. 1997, pp. 355-359. https://doi.org/10.1088/0268-1242/12/4/002
  27. O. Semenov, A. Vassighi, and M. Sachdev, "Leakage Current in Sub-quarter Micron MOSFET: a Perspective on Stressed Delta I DDQ Testing," J. Electron. Test., vol. 19, no. 3, June 2003, pp.341-352. https://doi.org/10.1023/A:1023713517064

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