• 산업경영시스템학회지
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• 제39권1호
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• pp.73-80
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• 2016

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

• 대한산업공학회지
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• 제35권4호
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• pp.266-279
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• 2009

This paper focuses on the problem of scheduling wafer lots with limited waiting times between pairs of consecutive operations in a semiconductor wafer fabrication facility. For the problem of minimizing total tardiness of orders, we develop a priority rule based scheduling method in which a scheduling decision for an operation is made based on the states of workstations for the operation and its successor or predecessor operation. To evaluate performance of the suggested scheduling method, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation experiments show that the suggested method performs better than a method suggested in other research and the one that has been used in practice.

• 대한산업공학회지
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• 제36권1호
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• pp.42-51
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• 2010

The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.

• 산업공학
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• 제10권1호
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• pp.1-13
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• 1997

반도체 Wafer Fabrication 공정은 무수한 공정과 복잡한 Lot의 흐름 등으로 다른 제조 형태에 비해 효율적인 관리가 대단히 어려운 부문이다. 본 연구는 반도체 Fab을 대상으로 주어진 생산 소요량과 목표 공기를 효율적으로 달성하기 위한 Shift 단위의 생산 일정계획을 대상으로 하였다. 특히, 전 공정 및 장비를 고려하기보다는 Bottleneck인 Photo 공정의 Stepper를 중심으로, 공정을 Layer단위로 묶어, 한 Shift에서 어떻게 Stepper를 할당하고 생산계획을 할 것인가를 결정하기 위한 2단계 방법론을 제시하고, Stepper 할당 및 계획에 필요한 3가지 알고리즘들을 제시하였다. 이 기법들을 소규모의 예제들에 대해 적용한 결과와 최적해와의 비교를 통하여 그 성능을 평가하였다.

• 대한기계학회논문집A
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• 제29권11호
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• pp.1463-1471
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• 2005

This paper proposes an agent-based scheduling method fur semiconductor wafer fabrication facilities with hard inter-operation temporal constraints. The scheduling problem is to find the feasible schedules that guarantee both logical and temporal correctness. A proposed multi-agent based architecture is composed of scheduling agents, workcell agents, and machine agents. A scheduling agent computes optimal schedules through bidding mechanisms with a subset or entire set of the workcell agents. A dynamic planning-based approach is adopted for the scheduling mechanism so that the dynamic behaviors such as aperiodic job arrivals and reconfiguration can be taken into consideration.

• 대한산업공학회지
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• 제36권2호
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• Composites Research
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• 제20권5호
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• pp.49-55
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• 2007

반도체 쿼츠 웨이퍼 다이싱용 블레이드는 마이크로/나노 디바이스와 부품을 제조하기 위해 고정밀도의 가공성을 요구한다. 따라서 균일한 마이크로/나노 선폭의 가공을 위해서는 블레이드의 제작 단계에서 균일한 두께와 밀도를 유지하는 것이 중요하다. 기존의 실리콘웨이퍼 가공을 위해서는 금속의 블레이드가 사용되고 있지만 쿼츠 웨이퍼 가공을 위해서는 고분자 복합재가 사용된다. 이러한 복합재는 가공성, 전기전도성, 그리고 적절한 강도와 연성 및 마모저항성이 있어야 한다. 그러나 기존의 건식성형 공정으로는 균일성을 유지하기 위해 많은 공정과 비용이 소비되고 있다. 본 연구에서는 도전성 나노 세라믹스 분말, 연마재 세라믹스 분말에 열경화성 수지, 전도성 고분자를 혼합한 복합재 분말을 습식성형 공정에 의해 제조, 평가하는 연구를 수행하였다. 먼저 복합재 분말을 액상과 혼합하여 블레이드를 제작하였으며, 액상의 종류, 액상 건조공정의 영향을 고찰하였다. 평가는 마이크로미터 측정기와 현미경을 이용하여 두께를 측정하였다. 두께편차와 기공률, 밀도, 경도, 등의 특성을 비교, 평가하였다. 그 결과 습식성형에 의해 블레이드의 두께편차를 감소시킬 수 있었으며, 경도 등의 특성을 향상시킬 수 있었다.

• 한국경영과학회:학술대회논문집
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• 대한산업공학회/한국경영과학회 1995년도 춘계공동학술대회논문집; 전남대학교; 28-29 Apr. 1995
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• pp.939-954
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• 1995

We propose a policy for controlling the release of raw wafers into the semiconductor wafer fabrication lines. The proposed policy exploits up-to-date factory floor information gathered by tracking systems used to calculate the time and amount of a new release to minimize mean flow times and mean tardiness while maintaining the maximum output rates of the system. Extensive computer experiments show that the proposed policy results in significant improvements for the same output rates compared to existing release rules.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2003년도 추계학술대회 및 정기총회
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• pp.147-151
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• 2003

Yield enhancement in semiconductor fabrication is important. Even though DRAM yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form patterns, it is usually an indication for the identification of equipment problems or process variations. In this paper describes the techniques to automatically classify a failure pattern using a fail bit map.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.401-406
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• 1988

Various types and huge volume of information such as process instructions, work-in process and parametric data are created in a wafer fabrication process and should be provided to personnels inside or outside the facility. This article describes design criteria and functional description on the information system for small-scale wafer fabrication process to accomplish paperless fab and to support efficient fab management.