A Scheduling Algorithm for Workstations with Limited Waiting Time Constraints in a Semiconductor Wafer Fabrication Facility

대기시간 제약을 고려한 반도체 웨이퍼 생산공정의 스케쥴링 알고리듬

  • 주병준 (LG전자 생산성연구원) ;
  • 김영대 (한국과학기술원 산업및시스템공학과) ;
  • 방준영 (한국과학기술원 산업및시스템공학과)
  • Received : 2009.08.12
  • Accepted : 2009.11.11
  • Published : 2009.12.31

Abstract

This paper focuses on the problem of scheduling wafer lots with limited waiting times between pairs of consecutive operations in a semiconductor wafer fabrication facility. For the problem of minimizing total tardiness of orders, we develop a priority rule based scheduling method in which a scheduling decision for an operation is made based on the states of workstations for the operation and its successor or predecessor operation. To evaluate performance of the suggested scheduling method, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation experiments show that the suggested method performs better than a method suggested in other research and the one that has been used in practice.

Keywords

References

  1. Anderson, E. J. and Nyirenda, J. C. (1990), Two New Rules to Minimize Tardiness in a Job Shop, International Journal of Production Research 28(12), 2277-2292 https://doi.org/10.1080/00207549008942866
  2. Artigues, C., Dauzere-Peres, S., Derreumaux, A., Sibille, O., and Yugma, C. (2006), A Batch Optimization Solver for Diffusion Area Scheduling in Semiconductor Manufacturing, Proc. 2006 IFAC International Symposium on Information Control Problems in Manufacturing 727-732
  3. Caumond, A. and Lacomme, P. (2008), A Memetic Algorithm for the Job-shop with Time-lags, Computers and Operational Research 35(7), 2331-2356 https://doi.org/10.1016/j.cor.2006.11.007
  4. Chen, J. S. and Yang, J. S. (2006), Model Formulations for the Machine Scheduling Problem with Limited Waiting Time Constraints, Jornal of Information and Optimization Sciences 27(1), 225-240 https://doi.org/10.1080/02522667.2006.10699688
  5. Chern C. C. and Huang, K. L. (2004), A Heuristic Input Control Method for a Single-product, High-volume Wafer Fabrication Process to Minimize the Number of Photomask Changes, Journal of Manufacturing Systems 23(1), 30-45 https://doi.org/10.1016/S0278-6125(04)80005-0
  6. Chun, K.-W. and Hong, Y. (1996), Batch Sizing Heuristic for Batch Processing Workstations in Semiconductor Manufacturing, Journal of the Korean Institute of Industrial Engineers 22(2), 231-245
  7. Dabbas R. M. and Fowler, J. W. (2003), A New Scheduling Approach using Combined Dispatching Criteria in Wafer Fabs, IEEE Transactions on Semiconductor Manufacturing 16(3), 501-510 https://doi.org/10.1109/TSM.2003.815201
  8. Duwayri, Z., Mollaghasemi, M., Nazzal, D., and Rabadi, G. (2006), Scheduling Setup Changes at Bottleneck Workstations in Semiconductor Manufacturing, Production Planning and Control 17(7), 717-727 https://doi.org/10.1080/09537280600901426
  9. Fondrevelle, J., Oulamara, A., and Portmann, M. C. (2006), Permutation Flowshop Scheduling Problems with Maximal and Minimal Time Lags, Computers and Operations Research 33(6), 1540-1556 https://doi.org/10.1016/j.cor.2004.11.006
  10. Fowler, J. W., Hogg, G. L., and Phillips, D. T. (2000), Control of Multiproduct Bulk Server Diffusion/oxidation Processes. Part 2: Multiple Servers, IIE Transactions 32(2), 167-176
  11. Garey, M. R. and Johnson, D. S. (1975), Complexity Results for Multiprocessor Scheduling Under Resource Constraints, SIAM Journal on Computing 4(4), 397-411 https://doi.org/10.1137/0204035
  12. Glassey, C. R. and Weng, W. W. (1991), Dynamic Batching Heuristic for Simultaneous Processing, IEEE Transactions on Semiconductor Manufacturing 4(2), 77-82 https://doi.org/10.1109/66.79719
  13. Gurnani, H., Anupindi, R., and Akella, R. (1992), Control of Batch Processing Systems in Semiconductor Wafer Fabrication Facilities, IEEE Transactions on Semiconductor Manufacturing 5(4), 319-328 https://doi.org/10.1109/66.175364
  14. Hodson, A., Muhlemann A. P., and Price, D. H. R. (1985), A Microcomputer based Solution to a Practical Scheduling Problem, Journal of the Operational Research Society 36(10), 903-914 https://doi.org/10.1057/jors.1985.160
  15. Hsieh, B.-W., Chen, C.-H., and Chang, S.-C. (2001), Scheduling Semiconductor Wafer Fabrication by using Ordinal Optimizationbased Simulation, IEEE Transactions on Robotics and Automation 17(5), 599-608 https://doi.org/10.1109/70.964661
  16. Hung, Y. F. (1998), Scheduling of Mask Shop E-beam Writers. IEEE Transactions on Semiconductor Manufacturing 11(1), 165-172 https://doi.org/10.1109/66.661296
  17. Johri, P. K. (1993), Practical Issues in Scheduling and Dispatching in Semiconductor Wafer Fabrication, Journal of Manufacturing Systems 12(6), 474-485 https://doi.org/10.1016/0278-6125(93)90344-S
  18. Joo, B.-J. and Kim, Y.-D. (2009), A Branch and Bound Algorithm for a Two-machine Flowshop Scheduling Problem with Limited Waiting Time Constraints, Journal of the Operational Research Society 60(4), 572-582 https://doi.org/10.1057/palgrave.jors.2602598
  19. Kim, Y.-D., Bang J.-Y., An K.-Y., and Lim, S.-K. (2008), A Due-date based Algorithm for Lot-order Assignment in a Semiconductor Wafer Fabrication Facility, IEEE Transactions on Semiconductor Manufacturing 21(2), 209-216 https://doi.org/10.1109/TSM.2008.2000261
  20. Kim, Y.-D., Kim, J.-G., Choi, B., and Kim, H.-U. (2001), Production Scheduling in a Semiconductor Wafer Fabrication Facility Producing Multiple Product Types with Distinct Due Dates, IEEE Transactions on Robotics and Automation 17(5), 589-598 https://doi.org/10.1109/70.964660
  21. Kim, Y.-D., Kim, J.-U., Lim, S.-K., and Jun, H.-B. (1998a), Due-date Based Scheduling and Control Policies in a Multiproduct Semiconductor Wafer Fabrication Facility, IEEE Transactions on Semiconductor Manufacturing 11(1), 155-164 https://doi.org/10.1109/66.661295
  22. Kim, Y.-D., Lee, D.-H., Kim, J.-U., and Roh, H.-K. (1998b), A Simulation Study on Lot Release Control, Mask Scheduling and Batch Scheduling in Semiconductor Wafer Fabrication Facilities, Journal of Manufacturing Systems 17(2), 107-117 https://doi.org/10.1016/S0278-6125(98)80024-1
  23. Kim, Y.-D., Shim, S.-O., Choi, B., and Hwang, H. (2003), Simplification Methods for Accelerating Simulation-based Realtime Scheduling in a Semiconductor Wafer Fabrication Facility, IEEE Transactions on Semiconductor Manufacturing 16(2), 290-298 https://doi.org/10.1109/TSM.2003.811890
  24. Kim, S., Yea, S.-H., Kim, B. (2002), Shift Scheduling for Steppers in the Semiconductor Wafer Fabrication Process, IIE Transactions 34(2), 167-177
  25. Kumar, P. R. (1994), Scheduling Semiconductor Manufacturing Plants, IEEE Control Systems 14(6), 33-40 https://doi.org/10.1109/37.334413
  26. Lee, G.-C., Kim, Y.-D., Kim, J.-G., Choi, S.-H. (2003), A Dispatching Rule-based Approach to Production Scheduling in a Printed Circuit Board Manufacturing System, Journal of the Operational Research Society 54(1), 1038-1049 https://doi.org/10.1057/palgrave.jors.2601601
  27. Lee, Y. H., Park, J., and Kim, S. (2002), Experimental Study on Input and Bottleneck Scheduling for a Semiconductor Fabrication Line, IIE Transactions 34(2), 179-190
  28. Li, S., Tang, T., Collins, D. W. (1996), Minimum Inventory Variability Schedule with Applications in Semiconductor Fabrication, IEEE Transactions on Semiconductor Manufacturing 9(1), 145-149 https://doi.org/10.1109/66.484296
  29. Liao, D.-Y., Chang S.-C., Pei, K.-W., and Chang, C.-M. (1996), Daily Scheduling for R&D Semiconductor Fabrication, IEEE Transactions on Semiconductor Manufacturing 9(4), 550-561 https://doi.org/10.1109/66.542170
  30. Lu, S. C. H., Ramaswamy, D., and Kumar, P. R. (1994), Efficient Scheduling Policies to Reduce Mean and Variance of Cycletime in Semiconductor Manufacturing Plants, IEEE Transactions on Semiconductor Manufacturing 7(3), 374-388 https://doi.org/10.1109/66.311341
  31. Min, H.-S. and Yih, Y. (2003), Selection of Dispatching Rules on Multiple Dispatching Decision Points in Real-time Scheduling of a Semiconductor Wafer Fabrication System, International Journal of Production Research 41(16), 3921- 3941 https://doi.org/10.1080/0020754031000118099
  32. Robinson, J. K. and Giglio, R. (1999), Capacity Planning for Semiconductor Wafer Fabrication with Time Constraints between Operations, Proc. 1999 Winter Simulation Conference, 880-887
  33. Scholl, W. and Domaschke, J. (2000), Implementation of Modeling and Simulation in Semiconductor Wafer Fabrication with Time Constraints between Wet Etch and Furnace Operations, IEEE Transactions on Semiconductor Manufacturing 13(3) 273-277 https://doi.org/10.1109/66.857935
  34. Sheen, G. J. and Liao, L. W. (2007), A Branch and Bound Algorithm for the One-machine Scheduling Problem with Minimum and Maximum Time Lags, European Journal of Operational Research 181(1), 102-116 https://doi.org/10.1016/j.ejor.2006.06.003
  35. Sloan. T. and Shanthikumar, J. G. (2002), Using In-line Equipment Condition and Yield Information for Maintenance Scheduling and Dispatching in Semiconductor Wafer Fabs, IIE Transactions 34(2), 191-209
  36. Sourirajan, K., Uzsoy, R. (2007), Hybrid Decomposition Heuristics for Solving Large-scale Scheduling Problems in Semiconductor Wafer Fabrication, Journal of Scheduling 10(1), 41-65 https://doi.org/10.1007/s10951-006-0325-5
  37. Su, L.-H. (2003), A Hybrid Two-stage Flowshop with Limited Waiting Time Constraints, Computers and Industrial Engineering 44(3), 409-424 https://doi.org/10.1016/S0360-8352(02)00216-4
  38. Upasani, A. A., Uzsoy, R., and Sourirajan, K. (2006), A Problem Reduction Approach for Scheduling Semiconductor Wafer Fabrication Facilities, IEEE Transactions on Semiconductor Manufacturing 19(2), 216-225 https://doi.org/10.1109/TSM.2006.873510
  39. Wein, L. M. (1988), Scheduling Semiconductor Wafer Fabrication, IEEE Transactions on Semiconductor Manufacturing 1(3), 115-130 https://doi.org/10.1109/66.4384
  40. Weng, W. W. and Leachman, R. C. (1993), An Improved Methodology for Real-time Production Decisions at Batch-process Work Stations, IEEE Transactions on Semiconductor Manufacturing 6(3), 219-225 https://doi.org/10.1109/66.238169
  41. Wikum, E. D., Llewellyn, D. C., and Nemhauser, G. L. (1994), One-machine Generalized Precedence Constrained Scheduling Problems, Operations Research Letters 16(2), 87-99 https://doi.org/10.1016/0167-6377(94)90064-7
  42. Yang, D.-L. and Chern, M.-S. (1995), Two-machine Flowshop Sequencing Problem with Limited Waiting Time Constraints, Computers and Industrial Engineering 28(1), 63-70 https://doi.org/10.1016/0360-8352(94)00026-J
  43. Yildirim, M. B., Duman, E., and Duman, D. (2006), Dispatching Rules for Allocation of Component Types to Machines in the Automated Assembly of Printed Circuit Boards, Lecture Notes in Computer Science 4263(1), 55-64