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Hexagonal Material Flow Pattern for Next Generation Semiconductor Fabrication  

Chung, Jae-Woo (School of Business Administration, Kyungpook National University)
Suh, Jung-Dae (Department of Industrial Engineering, Kyungwon University)
Publication Information
Journal of Korean Institute of Industrial Engineers / v.36, no.1, 2010 , pp. 42-51 More about this Journal
Abstract
The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.
Keywords
Semiconductor Wafer Fabrication; Semiconductor Facility Layout; Wafer Fabrication Layout;
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