1 |
Tompkins, J., White, J., Bozer, Y., and Tanchoco, J. (2003), Facilities Planning, John Wily and Sons, 3rd edition.
|
2 |
Turley, J. (2003), The essential guide to semiconductors, Prentice Hall, Upper Saddle River, NJ.
|
3 |
Pettinato, J. S. and Pillai, D. (2005), Technology decisions to minimize 450mm wafer size transition risk, 18(4).
|
4 |
Pillai, D. D., Bass, E. L., Dempsey, J. C., and Yellig, E. J. (2004), 300-mm full-factory simulations for 90-and 65-nm IC manufacturing, IEEE Transactions on Semiconductor Manufacturing, 17(3), 292-298.
DOI
ScienceOn
|
5 |
Quinn, T. and Bass, E. (1999), 300 mm factory layout and material handling modeling : phase I report, Technology Transfer # 99023688 B-ENG, International SEMATECH.
|
6 |
Singer, P. (2006), Transitioning to 450 mm wafers, Semiconductor International.
|
7 |
Newell, G. F. (1973), Scheduling, Location, Transportation, and Continuum Mechanics : Some Simple Approximations to Optimization Problems, SIAM Journal on Applied Mathematics, 25(3).
|
8 |
Montoya-Torres, J. R. (2007), Internal transport in automated semiconductor manufacturing systems : Novel approaches for tactical and operational management, Journal 4OR : A Quarterly Journal of Operations Research, 5(1), 93-97.
DOI
ScienceOn
|
9 |
Montoya-Torres, J. R., Dauzere-Peres, S., and Vermarien, L. (2006), A Consistent Approach for Vehicle Planning and Control in Large Unified Automated Material Handling Systems, 9th International Material Handling Research Colloquium.
|
10 |
Nazzal, D. and Mcginnis, L. F. (2007), Analytical approach to estimating AMHS performance in 300mm fabs, International Journal of Production Research, 45(3), 571-590.
DOI
ScienceOn
|
11 |
Noben, R., van Driel, R., and Claasen-Vujcic, T. (2001), Cycle time advantages of mini batch manufacturing and integrated metrology in a 300 mm vertical furnace, Semiconductor Manufacturing Symposium, 2001 IEEE International, 411- 414.
|
12 |
Lin, J. T., Wang, F. K., and Wu, C. K. (2003), Simulation analysis of the connecting transport AMHS in a wafer fab, IEEE Transactions on Semiconductor Manufacturing, 16(3), 555-564.
DOI
ScienceOn
|
13 |
Mackulak, G. T. and Savory, P. (2001), A simulation-based experiment for comparing AMHS performance in a semiconductor fabrication facility, IEEE Transactions on Semiconductor Manufacturing, 14(3), 273-280.
DOI
ScienceOn
|
14 |
Mackulak, G. T., Lawrence, F. P., and Colvin, T. (1998), Effective simulation model reuse : A case study for AMHS modeling, Winter Simulation Conference Proceedings, 2, 979-984.
|
15 |
Koike, A., Shimoyashiro, S., Kubota, K., Suzuki, N., Kiguchi, Y., Fujisawa, A., Takamatsu, A., and Okabe, T. (1995), A new LSI manufacturing scheme in the large-diameter wafer era for super-quick TAT development and volume production, Semiconductor Manufacturing, IEEE/UCS/SEMI International Symposium on, 239-242.
|
16 |
Montoya-Torres, J. R. (2006), A literature survey on the design approaches and operational issues of automated wafer-transport systems for wafer fabs, Production Planning and Control, 17(7), 648-663.
DOI
ScienceOn
|
17 |
Hopp, W. J., Spearman, M. L., Chayet, S., Donohue, K. L., and Gel, E. S. (2002), Using an optimized queueing network model to support wafer fab design, IIE Transactions, 34(2), 119-130.
|
18 |
Koike, A. (2000), A new fab concept in the 300 mm wafer era, Semiconductor Manufacturing, 2000. Proceedings of ISSM 2000. The Ninth International Symposium on, 44-47.
|
19 |
Lee, Y. H., Park, J., and Kim, S. (2001), Experimental study on input and bottleneck scheduling for a semiconductor fabrication line, IIE transactions, 34, 79-190.
|
20 |
Kong, S. H. (2007), Two-step simulation method for automatic material handling system of semiconductor fab, Robotics and Computer-Integrated Manufacturing, 23(4), 409-420.
DOI
ScienceOn
|
21 |
Fischmann, C., Bottinger, F., Wertz, R., and Kunz, C. (2008), Buffer Management For Automated Material Handling Systems In Semiconductor Industries, Proceedings 22nd European Conference on Modelling and Simulation.
|
22 |
Fowler, J. W., Hogg, G. L., and Mason, S. J. (2002), Workload control in the semiconductor industry, Production Planning and Control, 13(7), 568-578.
DOI
ScienceOn
|
23 |
Connors, D. P., Feigin, G. E., and Yao, D. D. (1996), Queueing network model for semiconductor manufacturing, IEEE Transactions on Semiconductor Manufacturing, 9(3), 412-427.
DOI
ScienceOn
|
24 |
Geiger, C. D., Hase, R., Takoudis, C. G., and Uzsoy, R. (1997), Alternative facility layouts for semiconductor wafer fabrication facilities, IEEE Transactions on Components, Packing, And Manufacturing Technology-Part C, 20(2), 152-163.
|
25 |
Hase, R., Takoudis G., and Uzsoy R. (1994), Cellular and reentrant layouts for semiconductor wafer fabrication facilities, IEEE/CPMT international electronics manufacturing technology symposium, 112-118.
|
26 |
Chen, H., Harrison, J. M., Mandelbaum, A., Ackere, A. V., and Wein, L. M. (1988), Empirical evaluation of a queueing network model for semiconductor wafer fabrication, Operations Research, 36(2), 202-215.
DOI
ScienceOn
|
27 |
Chung, J. and Jang, J. (2007), The integrated room layout, IEEE Transactions on Semiconductor Manufacturing, 20(4), 517-527.
DOI
|
28 |
Chung, J. and Tanchoco, J. M. A., Layout Design with Hexagonal Floor Plans and Material Flow Patterns, International Journal of Production Research, Forthcoming.
|
29 |
Eppen, G. (1979), Effects of Centralization on Expected Costs in a Multi- Location Newsboy Problem, Management Science, 25(5), 498-501.
DOI
ScienceOn
|
30 |
Campbell, E. and Ammenheuser, J. (2000), 300 mm factory layout and material handling modeling : phase II report, Technology transfer, # 99113848B-ENG, International SEMATECH.
|