Automatic classify of failure patterns in semiconductor fabrication for yield improvement

수율 향상을 위한 반도체 공정에서의 불량 유형 자동 분류

Yield enhancement in semiconductor fabrication is important. Even though DRAM yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form patterns, it is usually an indication for the identification of equipment problems or process variations. In this paper describes the techniques to automatically classify a failure pattern using a fail bit map.