• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.690-692
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• 2012

This pape presents the efficient test data compression method considering test power dissipation in scan test of IP core. There are many researches about test data compression using scan slice selective encoding except power dissipation. We present the new algorithm that assigns the don't care value to be a minimal hamming distance between adjacent slices. Experimental results show that the power dissipation is reduced.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.11
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• pp.637-642
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• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.12
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• pp.675-682
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• 2000

When a system is composed of multi-boards, an efficient bus arbitration method for the data transfer bus must be provided for guaranteeing proper operations. In this paper, a new test methodology is developed which is used for testing on-line bus arbitration. In the new test methodology, events that are occurred during bus arbitration are defined, and expected signals during fault-free bus arbitration are compared with the signals captured during on-line bus arbitration using boundary-scan cells. For this, a new test architecture is proposed which is efficient for the maintenance and the repair of multi-board systems. In addition, the new methodology can be used with off-line interconnect test using boundary-scan.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1924-1937
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• 1996

In this paper, we propose a ESP(Extended Scan Path) architecture for multi- board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan paths either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using, he proposed ESP architecture, we observed to the test time is short compared with the single scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS '85 bench mark circuit, we showed that the architecture has improved results.

• Journal of Korea Multimedia Society
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• v.4 no.6
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• pp.570-578
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• 2001

Boundary scan architecture test methodology was introduced to facilitate the testing of complex printed circuit board. The boundary scan architecture has a tremendous potential for real time monitoring of the operational status of a system without interference of normal system operation. In this paper, a new type of embedded controller for real time monitoring of the operational status of a system is proposed and designed by using boundary scan architecture. The proposed real time monitoring embedded controller consists of test access port controller and an embedded controller proposed real time monitoring embedded controller using boundary scan architecture can save the hard-wire resource and can easily interface with boundary scan architecture chip. Experimental results show that the real time monitoring using proposed embedded controller is more effective then the real time monitoring using host computer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.45-54
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• 2002

This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1045-1054
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• 2002

We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.45-51
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• 2003

In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.

• The Journal of Advanced Prosthodontics
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• v.14 no.5
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• pp.294-304
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• 2022

PURPOSE. The purpose of this study was to evaluate the influence of different palatal vault configurations on the accuracy and scan speed of intraoral scans (IO) of completely edentulous arches. MATERIALS AND METHODS. Three different virtual models of a completely edentulous maxillary arch with different palatal vault heights- Cl I moderate (U-shaped), Cl II deep (steep) and Cl III shallow (flat)-were digitally designed using CAD software (Meshmixer; Autodesk, USA) and 3D-printed using SLA-based 3D-printer (XFAB; DWS, Italy) (n = 30; 10 specimens per group). Each model was scanned using intraoral scanner (Trios 3; 3Shape^TM, Denmark). Scanning time was recorded for all samples. Scanning accuracy (trueness and precision) were evaluated using digital subtraction technique using Geomagic Control X v2020 (Geomagic; 3DSystems, USA). One-way analysis of variance (ANOVA) test was used to detect differences in scanning time, trueness and precision among the test groups. Statistical significance was set at α = .05. RESULTS. The scan process could not be completed for Class II group and manufacturer's recommended technique had to be modified. ANOVA revealed no statistically significant difference in trueness and precision values among the test groups (P=.959 and P=.658, respectively). Deep palatal vault (Cl II) showed significantly longer scan time compared to Cl I and III. CONCLUSION. The selection of scan protocol in complex cases such as deep palatal vault is of utmost importance. The modified, adopted longer path scan protocol of deep vault cases resulted in increased scan time when compared to the other two groups.