Browse > Article

A Study on Efficient Test Data Compression Method for Test-per-clock Scan  

Park, Jae-Heung (Department of Computing, Graduate School, Soongsil University)
Yang, Sun-Woong (Department of Computing, Graduate School, Soongsil University)
Chang, Hoon (School of Computing, Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.9, 2002 , pp. 45-54 More about this Journal
Abstract
This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.
Keywords
scan; test-per-clock; DFT; data compression; SOC;
Citations & Related Records
연도 인용수 순위
  • Reference
1 http://www.ee.vt.edu/ha/
2 I. Hamazaoglu, J. H. Patel, 'Test Set Compaction Algorithms for Combinational Circuits,' Proceedings of International Conference on Computer-Aided Design, November, pp. 283-289, 1998
3 A. Chandra and K. Chakrabarty, 'Test Data Compression for System-On-a-Chip using Golomb Codes,' Proceedings of VLSI Test Symposium, pp. 113-120, 2000   DOI
4 http://cbl.ncsu.edu/CBL_Docs/iscas89.html
5 R. Garey and S. Johnson, Computers and Intractability, a guide to the theory of NP-completeness, Freeman and Company, 1991
6 J. B. Kruskal, 'On the shortest spanning subtree of a graph and the traveling salesman problem,' Proceedings of American Mathematical Society, Volume 7, Number 1, pp. 48-50, 1956   DOI
7 http://cbl.ncsu.edu/CBL_Docs/iscas85.html
8 Y. Zorian, 'Test Requirements for Embedded Core-based Systems and IEEE P1500,' Proceedings of International Test Conference, pp. 191-199, 1997   DOI
9 Y. Zorian, E.J. Marinissen, and S. Dey, 'Testing Embedded-Core Based System Chips,' Proceedings of International Test Conference, pp. 130-143, 1998   DOI
10 A EI-Maleh, S. al Zahir and E. Khan, 'A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip,' Proceedings of VLSI Test Symposium, pp. 54-59, 2001   DOI
11 K. Chakrabarty, B.T. Murray, J. Liu, and M. Zhu, 'Test Width Compression for Built-In Self-Testing,' Proceedings of International Test Conference, pp. 328-337, 1997   DOI
12 J. Rajski, J. Tyszer, and N. Zaccharia, 'Test Data Decompression for Multiple Scan Designs with Boundary Scan,' IEEE Transactions on Computers, Volume 47, Issue 11, pp. , 1998   DOI   ScienceOn
13 M. Ishida, D. S. Ha, and T. Yamaguchi, 'Compact: A hybrid method for compressing test data,' In Proceedings IEEE VLSI Test Symposium, pp. 62 - 69, 1998   DOI