The Transactions of the Korean Institute of Electrical Engineers D (대한전기학회논문지:시스템및제어부문D)

The Korean Institute of Electrical Engineers (대한전기학회)
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New IEEE 1149.1 Boundary Scan Architecture for Multi-drop Multi-board System

멀티 드롭 멀티 보드 시스템을 위한 새로운 IEEE 1149.1 경계 주사 구조

  • 배상민 (연세대 공대 전기전자공학과) ;
  • 송동섭 (연세대 공대 전기전자공학과) ;
  • 강성호 (연세대 공대 전기전자공학과) ;
  • 박영호 (한국전자통신연구원)
  • Published : 2000.11.01
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Abstract

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

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References

  1. K. P. Parker The Boundary-Scan Handbook, Kluwer Academic Publishers, 1992
  2. Texas Instruments IEEE Std 1149.1 (JTAG) Testability, Semiconductor Group, 1997
  3. A. Hassan, J. Rajski, V. K. Agarwal 'Testing and Diagnose of Interconnects using Boundary Scan Architecture', Proc. of International Test Conference, pp. 126-137, 1998 https://doi.org/10.1109/TEST.1988.207790
  4. L. Whetsel, 'Hierarchically Accessing 1149.1 Applications in a System Environment', Proc. of International Test Conference, pp. 517-526, 1993
  5. C. Su, S. Jou, and Y. T. Ting, 'Decentralized BIST for 1149.1 and 1149.5 Based Interconnects', Proc. of European Design and Test Conference, pp. 120-125, 1996
  6. C. Su, and Y. T. Chen, 'Comprehensive Interconnect BIST Methodology for Virtual Socket Interface', Proc. of Asian Test Symposium, pp. 259-263, 1998 https://doi.org/10.1109/ATS.1998.741622
  7. C. Su, and Y. T. Chen, 'Boundary Scan BIST Methodology for Reconfigurable Systems', Proc. of International Test Conference, pp. 774-782, 1998 https://doi.org/10.1109/TEST.1998.743260