Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A Study on Efficient Test Data Compression Method for Test-per-clock Scan

Test-per-clock 스캔 방식을 위한 효율적인 테스트 데이터 압축 기법에 관한 연구

  • Park, Jae-Heung (Department of Computing, Graduate School, Soongsil University) ;
  • Yang, Sun-Woong (Department of Computing, Graduate School, Soongsil University) ;
  • Chang, Hoon (School of Computing, Soongsil University)
  • 박재흥 (崇實大學校 컴퓨터學科) ;
  • 양선웅 (崇實大學校 컴퓨터學科) ;
  • 장훈 (崇實大學校 컴퓨터學部)
  • Published : 2002.09.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.

P45 본 논문에서는 SOC의 내장된 코어를 테스트하기 위한 새로운 DFT 방법인 순차적 테스트 데이터 압축 방법을 제안한다. 순차적 테스트 데이터 압축 방법은 테스트 데이터양을 줄이기 위하여 공유 비트 압축과 고장 무검출 패턴 압축 방법을 이용하였다. 그리고 순차적 테스트 데이터 압축 방법을 이용하는 회로는 스캔 DFT 방법을 기반으로 하고 있으며, test-per-clock 방법을 적용하여 매 클럭마다 테스트 할 수 있는 구조를 가지고 있다. 제안된 압축 방법의 실험을 위하여 벤치마크 회로인 ISCASS85와 ISCASS89 완전 스캔 버전을 이용하였으며, ATPG와 고장 시뮬레이션을 위하여 ATALANTA를 사용하였다. 실험 결과 순차적 테스트 데이터 압축 방법의 테스트 데이터의 양이 스캔 DFT를 적용한 회로에 비해 최대 98% 까지 줄어듦을 확인하였다.

Keywords

References

  1. Y. Zorian, 'Test Requirements for Embedded Core-based Systems and IEEE P1500,' Proceedings of International Test Conference, pp. 191-199, 1997 https://doi.org/10.1109/TEST.1997.639613
  2. Y. Zorian, E.J. Marinissen, and S. Dey, 'Testing Embedded-Core Based System Chips,' Proceedings of International Test Conference, pp. 130-143, 1998 https://doi.org/10.1109/TEST.1998.743146
  3. A EI-Maleh, S. al Zahir and E. Khan, 'A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip,' Proceedings of VLSI Test Symposium, pp. 54-59, 2001 https://doi.org/10.1109/VTS.2001.923418
  4. K. Chakrabarty, B.T. Murray, J. Liu, and M. Zhu, 'Test Width Compression for Built-In Self-Testing,' Proceedings of International Test Conference, pp. 328-337, 1997 https://doi.org/10.1109/TEST.1997.639634
  5. J. Rajski, J. Tyszer, and N. Zaccharia, 'Test Data Decompression for Multiple Scan Designs with Boundary Scan,' IEEE Transactions on Computers, Volume 47, Issue 11, pp. , 1998 https://doi.org/10.1109/12.736428
  6. M. Ishida, D. S. Ha, and T. Yamaguchi, 'Compact: A hybrid method for compressing test data,' In Proceedings IEEE VLSI Test Symposium, pp. 62 - 69, 1998 https://doi.org/10.1109/VTEST.1998.670850
  7. R. Garey and S. Johnson, Computers and Intractability, a guide to the theory of NP-completeness, Freeman and Company, 1991
  8. J. B. Kruskal, 'On the shortest spanning subtree of a graph and the traveling salesman problem,' Proceedings of American Mathematical Society, Volume 7, Number 1, pp. 48-50, 1956 https://doi.org/10.2307/2033241
  9. http://cbl.ncsu.edu/CBL_Docs/iscas85.html
  10. http://cbl.ncsu.edu/CBL_Docs/iscas89.html
  11. http://www.ee.vt.edu/ha/
  12. I. Hamazaoglu, J. H. Patel, 'Test Set Compaction Algorithms for Combinational Circuits,' Proceedings of International Conference on Computer-Aided Design, November, pp. 283-289, 1998
  13. A. Chandra and K. Chakrabarty, 'Test Data Compression for System-On-a-Chip using Golomb Codes,' Proceedings of VLSI Test Symposium, pp. 113-120, 2000 https://doi.org/10.1109/VTEST.2000.843834