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The Scan-Based BIST Architecture for Considering 2-Pattern Test  

손윤식 (한양대학교 전자공학과)
정정화 (한양대학교 전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.10, 2003 , pp. 45-51 More about this Journal
Abstract
In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.
Keywords
BIST; MISR; Signature; STUMPS;
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