• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.2
• /
• pp.182-187
• /
• 1988

Hot carrier induced device degradation characteristics under DC bias stress have been investigated in n-MOSFETs with channel length of 1.2,1.8 um, and compared with those of LDD structure device with same channel length. Based on these results, the device lifetime in normal operating bias(Vgs=Vds=5V) is evaluated. The lifetimes of conventional and LDD n-MOSFET with channel length of 1.2 um are estimated about for 17 days and for 12 years, respectively. The degradation rate of LDD n-MOSFET under the same stress is the lowest at n-region implnatation dose of 2.5E15 cm-\ulcorner while the substrate current is the lowest at the dose of 1E13cm-\ulcorner Thses results show that the device degradation characteristics are basic measurement parameter to find optimum process conditions in LDD devices and evaluate a reliability of sub-micron device.

• Journal of the Semiconductor & Display Technology
• /
• v.13 no.3
• /
• pp.45-50
• /
• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.32 no.2
• /
• pp.104-109
• /
• 2019

An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.9
• /
• pp.1771-1777
• /
• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.11
• /
• pp.45-55
• /
• 1999

The small signal analyzer for the stationary drift-diffusion equation is developed. The slotboom variables of the potential, electron and hole concentrations for the response of applied small signal are defined and the stationary drift-diffusion equation is linearlized on DC operation point by $S^3A$ method. Frontal solver, which is used to solve the global matrix, progresses the accuracy of the solution in high frequency and minimizes the requirement of the memory. The simulations are executed on the structure of 3 dimensional N'P junction diode and 2 dimensional n-MOSFET to verify the proposed algorithm. The average relative errors of the conductance and the capacitance compared with MEDICI are about 26% and 0.67 for N'P junction diode and 7.75% and 2.24% for n-MOSFET. The simulation by the proposed algorithm can analyze the stationary drift-diffusion equation for applied small signal in high frequency region about 100GHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.1
• /
• pp.83-88
• /
• 2007

The reliability characteristics of class-E RF power amplifier are studied, based on the degradation of MOSFET electrical characteristics. The class-E power amplifier operates as a switch mode operation to achieve high efficiency. This operation leads to high voltage stress when MOSFET switch is turned-off. The increase in threshold voltage and decrease in nobility caused by high voltage stress leads to a drop in the drain current. In the class-E power amplifier the effects caused by the degradation of MOSFET drain current is a drop of the power efficiency and output power. But the small inductor in the class-E load network allows the reliability to be improved. After $10^{7}\;sec$. the drain current decreases 46.3% and the PAE(Power Added Efficiency) decreases from 58% to 36% when the load inductor is 1mH. But when the load inductor is 1nH the drain current decreases 8.89% and the PAE decreases from 59% to 55%.

• Proceedings of the KIEE Conference
• /
• 1987.11a
• /
• pp.193-196
• /
• 1987

We reported that hot electron phenomena in submicron nMOSFET by Monte Carlo method. In order to predict the influence of the hot electron effects on the device reliability, either simple analytical model or a complete two dimensional numerical simulation has been adopted. Results of numerical simulation, based on the static mobility model, may be inaccurate when gate length of MOSFET is scaled down to less than 1um. Most of device simulation packages utilize the static nobility model. Monte Carlo method based on stochastic analysis of carrier movement may be a powerful tool to characterize hot electrons. In this work, energy and velocity distribution of carriers were obtained to predict the relative degree of short channel effects for different device parameters. Our analysis shows a few interesting results when $V_{ds}$ is 5 volt, average electron energy does not increase with gate bias as evidenced by substrate current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.24 no.9
• /
• pp.713-717
• /
• 2011

This paper was carried out design of 600 V GaN power MOSFET Modeling. We decided trench gate type one for design. we carried out device and process simulation with T-CAD tools. and then, we have extracted optimal device and process parameters for fabrication. we have analysis electrical characteristics after simulations. As results, we obtained 600 V breankdown voltage and $0.4\;m{\Omega}cm^2ultra$ low on resistance. At the same time, we carried out field ring simulation for obtaining high voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.10a
• /
• pp.480-484
• /
• 2000

The channel length influence of n-channel Si-based FETs is investigated by computer simulation. Using a two-dimensional hydrodynamic model, devices having various gate length are examined. We have observed the characteristics of LDD model of MOSFET by investigating of their current, voltage, electric field and impact ionization. These devices are scaled using various factors. We have analyzed I-V characteristics and the effect of impact ionization according to channel length.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.27 no.8
• /
• pp.497-500
• /
• 2014

In this paper, we analyze electrical characteristics of n/p-pillar layer according to trench angle which is the most important characteristics of SJ MOSFET and core process. Because research target is 600 V class SJ MOSFET, so conclusively trench angle deduced 89.5 degree to implement the breakdown voltage 750 V with 30% margin rate. we found that on resistance is $22mohm{\cdot}cm^2$ and threshold voltage is 3.5 V. Moreover, depletion layer of electric field distribution also uniformly distributes.