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http://dx.doi.org/10.4313/JKEM.2019.32.2.104

Analysis of Threshold Voltage Roll-Off and Drain Induced Barrier Lowering in Junction-Based and Junctionless Double Gate MOSFET  

Jung, Hak Kee (Department of Electronic Engineering, Kunsan National University)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.32, no.2, 2019 , pp. 104-109 More about this Journal
Abstract
An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.
Keywords
Junction-based; Junctionless; Threshold voltage; DIBL; Threshold voltage roll-off;
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