Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

Breakdown Characteristics of Silicon Nanowire N-channel GAA MOSFET

실리콘 나노와이어 N-채널 GAA MOSFET의 항복특성

  • Ryu, In Sang (Department of Electronic Engineering, Incheon National University) ;
  • Kim, Bo Mi (Department of Electronic Engineering, Incheon National University) ;
  • Lee, Ye Lin (Department of Electronic Engineering, Incheon National University) ;
  • Park, Jong Tae (Department of Electronic Engineering, Incheon National University)
  • Received : 2016.06.10
  • Accepted : 2016.07.21
  • Published : 2016.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

본 논문에서는 나노와이어 N-채널 GAA MOSFET의 항복전압 특성을 측정과 3 차원 소자 시뮬레이션을 통하여 분석하였다. 측정에 사용된 나노와이어 GAA MOSFET는 게이트 길이가 250nm이며 게이트 절연층 두께는 6nm이며 채널 폭은 400nm부터 3.2um이다. 측정 결과로부터 나노와이어 GAA MOSFET의 항복전압은 게이트 전압에 따라 감소하다가 높은 게이트 전압에서는 증가하였다. 나노와이어의 채널 폭이 증가할수록 항복전압이 감소한 것은 floating body 현상으로 채널의 포텐셜이 증가하여 기생 바이폴라 트랜지스터의 전류 이득이 증가한 것으로 사료된다. 게이트 스트레스로 게이트 절연층에 양의 전하가 포획되면 채널 포텐셜이 증가하여 항복전압이 감소하고 음의 전하가 포획되면 포텐셜이 감소하여 항복전압이 증가하는 것을 알 수 있었다. 항복전압의 측정결과는 소자 시뮬레이션의 포텐셜 분포와 일치하는 것을 알 수 있었다.

Keywords

References

  1. J. T. Park, and J. P. Colinge, "Multiple gate SOI MOSFETs :Device design guidelines," IEEE Transactions on Electron Devices, vol. 49, no.12, pp. 2222-2228, Dec. 2002. https://doi.org/10.1109/TED.2002.805634
  2. J. P. Colinge, "Multiple-gate SOI MOSFETs," Solid-state Electronics, vol.48, no.6, pp.897-905, June 2004. https://doi.org/10.1016/j.sse.2003.12.020
  3. M.D. Marchi, D. Sacchetto, J. Zhang, S. Frache, P. Gaillardon, Y. Leblebici, G.D. Micheli, "Top-down fabrication of gate-all-around vertically stacked silicon nanowire FETs with controllable polarity," IEEE Trans on Nanotechnology, vol.13, no.6, pp. 1029-1038, Nov. 2014. https://doi.org/10.1109/TNANO.2014.2363386
  4. M. Aoulaiche, N. Collaert, R. Degraeve, Z. Lu, B.D. Wachter, G. Groeseneken, M. Jurczak, and L. Altimime. "BJT-mode endurance on 1T-DRAM bulk FinFET device," IEEE Electron Device Letters, vol. 31, no. 12, pp. 1380-1382, Dec. 2010. https://doi.org/10.1109/LED.2010.2079313
  5. C.W. Lee, A. Afzalian, R. Yan, N.D. Akhavan, W. Xiong, and J.P. Colinge, "Drain breakdown voltage in MuGFETs: influence of physical parameters," IEEE Trans Electron Dev., vol. 55, no. 12, pp. 3503-3506, Dec. 2008. https://doi.org/10.1109/TED.2008.2006546
  6. J.G. Fossum, J.Y. Oh, and R. Sundaresan, "SOI design for competitive CMOS VLSI," IEEE Trans Electron Dev. vol. 37, No.3, pp. 3503-3506, March 1990.
  7. N. Kistler, E. V. Ploeg, J. Woo, and J. Plummer, "Dependence of fully depleted SOI MOSFET breakdown on film thickness and channel length," in Proc. of IEEE Int. SOI Conf., pp.128-129, 1992.
  8. H. Kufluoglu, and M.A. Alam, "Theory of Interface trap Induced NBTI degradation for reduced cross section MOSFETs," IEEE Trans. Electron Devices, vol.53, no.5, pp.1120-1130, May 2006. https://doi.org/10.1109/TED.2006.872098
  9. J.Y. Kim, C.H. Yu, and J. T. Park, "Effects of device layout on the drain breakdown voltage in MuGFETs," Microelectronics Reliability, vol. 51, no. 9-11, pp.1547-1550, Sep. 2011. https://doi.org/10.1016/j.microrel.2011.07.010
  10. S. M. Lee, C.G. Yu, S. M. Jeong, W.J. Cho, and J.T. Park, "Drain breakdown voltage: A comparison between junctionless and inversion mode p-channel MOSFETs," Microelectronics Reliability, vol.52, no.9-11, pp.1945-1948, Sep. 2012. https://doi.org/10.1016/j.microrel.2012.06.018
  11. D. Moon, S. Choi, C. Kim, J. Kim, J. Lee, and J. Oh, "Silicon Nanowire All-Around Gate MOSFETs Built on a Bulk Substrate by All Plasma-Etching Routes," IEEE Electron Device Letters, vol.30, no.4, pp.452-454, Apr. 2011.
  12. Silvaco TCAD ATLAS(3D) Tools [Internet]. Available: http://www.silvaco.com/products/tcad/device_simulation/device_simulation.html.
  13. D. K. Schroder, Semiconductor material and device characterization, New York, NY : A Wiley-Interscience Publication, p.185, 1990.
  14. K. K. Young, and J. A. Burns, "Avalanche induced drainsource breakdown in silicon-on-insulator n-MOSFET's," IEEE Trans Electron Dev., vol. 35, no.4, pp. 426-431, Apr. 1998.
  15. Y. Tar, and T.H. Ning, Fundamental of modern VLSI Devices, Cambridge, U.K.: Cambridge University Press, p.347, 1998.