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Simulation Studies on the Super-junction MOSFET fabricated using SiGe epitaxial process  

Lee, Hoon-Ki (School of Semiconductor and Chemical Engineering, Semiconductor Physic Research Center, (SPRC), Chonbuk National University)
Park, Yang-Kyu (School of Semiconductor and Chemical Engineering, Semiconductor Physic Research Center, (SPRC), Chonbuk National University)
Shim, Kyu-Hwan (School of Semiconductor and Chemical Engineering, Semiconductor Physic Research Center, (SPRC), Chonbuk National University)
Choi, Chel-Jong (School of Semiconductor and Chemical Engineering, Semiconductor Physic Research Center, (SPRC), Chonbuk National University)
Publication Information
Journal of the Semiconductor & Display Technology / v.13, no.3, 2014 , pp. 45-50 More about this Journal
Abstract
In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.
Keywords
Super-junction MOSFET; SiGe; P-pillar; N-pillar; breakdown voltage; drain current;
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