• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.152-157
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• 2015

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

• 전기학회논문지P
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• 제60권3호
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• pp.126-132
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• 2011

A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP's DC Gain and Bandwidth can't optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can't improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6mV/V, 0.25mV/mA, respectively. And measured settling time is 1.5us in 5V supply voltage.

• 전기전자학회논문지
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• 제20권3호
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• pp.318-321
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• 2016

IoT 산업이 빠르게 성장하면서 전원 관리 집적회로의 중요성이 부각되고 있다. 본 논문에서는 리플 Subtractor, 피드 포워드 커패시터, OTA를 이용한 LDO 구조를 제안한다. 이를 통해 10MHz가 넘는 고주파 영역에서도 -40dB 이상 높은 전원 전압 제거비(PSRR)를 얻었다. 설계된 Low-Dropout(LDO) 레귤레이터는 $0.18{\mu}m$ CMOS 공정에서 설계되었으며 시뮬레이션 결과 PSRR은 부하 전류 40mA, 500kHz에서 -73.4dB다. 최대 구동 가능 전류는 40mA이다.

• ETRI Journal
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• 제42권5호
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.263-271
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• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.

• 한국정보통신학회논문지
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• 제22권7호
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• pp.993-1000
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• 2018

본 논문에서는 셀프-캐스코드 구조를 이용한 LDO 레귤레이터를 제안하였다. 셀프-캐스코드 구조의 소스 측 MOSFET의 채널 길이를 조절하고, 드레인 측 MOSFET의 바디에 순방향 전압을 인가함으로써 최적화하였다. 오차 증폭기 입력 차동단의 셀프-캐스코드 구조는 높은 트랜스컨덕턴스를 가지도록, 출력단은 높은 출력 저항을 가지도록 최적화하였다. 제안 된 LDO 레귤레이터는 $0.18{\mu}m$ CMOS 공정을 사용하였고, SPECTERE를 이용하여 시뮬레이션 되었다. 제안 된 셀프-캐스코드 구조를 이용한 LDO 레귤레이터의 로드 레귤레이션은 0.03V/A로 기존 LDO의 0.29V/A보다 급격하게 개선되었다. 라인 레귤레이션은 2.23mV/V로 기존 회로보다 약 3배 향상되었다. 안정화 속도는 625ns로 기존 회로보다 346ns 개선되었다.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• ETRI Journal
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• 제37권5호
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• pp.961-971
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• 2015

This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a$0.11{\mu}m$ CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at $20{\mu}A$ to $200{\mu}A$ load current.

• ETRI Journal
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• 제32권4호
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• pp.520-529
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• 2010

In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop-out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.

• Transactions on Electrical and Electronic Materials
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• 제18권5호
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• pp.257-260
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• 2017

In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.