1 |
L. G. Salem, J. Warchall, and P. P. Mercier, A 100 nA-to-2 mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1 ns response time at 0.5 V, in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 2017, pp. 5-9.
|
2 |
Y.-J. Lee et al., A 200 mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors, IEEE J. Solid-State Circuits 52 (2017), no. 1, 64-76.
DOI
|
3 |
M. Huang et al., A fully integrated digital LDO with coarse fine tuning and burst-mode operation, IEEE Trans. Circuits Syst. II: Express Briefs 63 (2016), no. 7, 683-687.
DOI
|
4 |
M.-A. Akram, W. Hong, and I.-C. Hwang, Fast transient fully standard cell-based all digital low-dropout regulator with 99.97% current efficiency, IEEE Trans. Power Electron. 33 (2018), no. 9, 8011-8019.
DOI
|
5 |
K.-C. Woo et al., A fast-transient digital LDO using a double edge-triggered comparator with a completion signal, in Proc. Int. Conf. Electron., Inf., Commun., Honolulu, HI, 2018, pp. 1-4.
|
6 |
A. Singh et al., A digital low-dropout regulator with auto-tuned PID compensator and dynamic gain control for improved transient performance under process variations and aging, IEEE Trans. Power Electron. 35 (2020), no. 3, 3242-3253.
DOI
|
7 |
T.-J. Oh and I.-C. Hwang, A 110-nm CMOS 0.7-V input transient- enhanced digital low-dropout regulator with 99.98% current efficiency at 80-mA Load, IEEE Trans. Very Large Scale Integr. Syst. 23 (2015), 1281-1286.
DOI
|
8 |
K.-C. Woo and B.-D Yang, A digital low-dropout regulator with a voltage differential detector for removing transient oscillation, J. Semiconductor Technol. Sci. 19 (2019), 492-497.
DOI
|
9 |
Y. Okuma et al., 0.5-V input digital LDO with 98.7% current efficiency and 2.7- A quiescent current in 65 nm CMOS, Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, USA, Sept. 2010, pp. 1-4.
|
10 |
D. Kim and M. Seok, Fully integrated low-drop-out regulator based on event-driven pi control, in Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 2016, pp. 148-149.
|
11 |
C. Y. Lim et al., A 50-mA 99.2% peak current efficiency, 250-ns settling time digital low-dropout regulator with transient enhanced PI controller, IEEE Trans. Very Large Scale Integr. Syst. 25 (2017), no. 8, 2360-2370.
DOI
|
12 |
J.-H. Lin et al., A digital low-dropout-regulator with steady-state load current (SLC) estimator and dynamic gain scaling (DGS) control, in Proc. IEEE Asia Pacific Conf. Circuits Syst., Jeju, Rep. of Korea, 2016, pp. 25-28.
|