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http://dx.doi.org/10.5370/KIEEP.2011.60.3.126

A Design of LDO(Low Dropout Regulator) with Enhanced Settling Time and Regulation Property  

Park, Kyung-Soo (한양대 공대 전자컴퓨터통신공학과)
Park, Jea-Gun (한양대 공대 전자컴퓨터통신공학과)
Publication Information
The Transactions of the Korean Institute of Electrical Engineers P / v.60, no.3, 2011 , pp. 126-132 More about this Journal
Abstract
A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP's DC Gain and Bandwidth can't optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can't improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6mV/V, 0.25mV/mA, respectively. And measured settling time is 1.5us in 5V supply voltage.
Keywords
LDO; Line Regulation; Load Regulation; Reference Source; Settling Time;
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