• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.287-298
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• 2007

A two-dimensional treatment of the potential distribution under the depletion approximation is presented for poly-crystalline silicon thin film transistors. Green's function approach is adopted to solve the two-dimensional Poisson's equation. The solution for the potential distribution is derived using Neumann's boundary condition at the silicon-silicon di-oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain-boundaries. Also short-channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.2
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• pp.104-109
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• 2019

An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1357-1359
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• 2001

0.2${\mu}m$ 이하의 최소 선폭을 가지는 소자를 구현할 때 drain induced barrier lowering (DIBL)이나 hot electron effect와 같은 short channel effect (SCE)가 나타나며 이로 인하여 소자의 신뢰성이 악화되기도 한다. 이를 개선하기 위한 방법 중 하나가 silicon selective epitaxial growth (SEG)를 이용한 elevated source/drain (ESD) 구조이다. 본 연 구에서는 silicon selective epitaxial growth를 이용하여 elevated source/drain 구조를 갖는 MOSFET 소자와 일반적인 MOSFET 구조를 갖는 소자와의 차이를 elevated source/drain의 높이 변화에 따른 전류 전압 특성을 이용하여 비교, 분석하였으며 그 결과 elevated source/drain 구조가 short channel effect를 감소시킴을 확인할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.390-397
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• 2001

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.434-438
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• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.683-685
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• 2012

This paper have presented the analysis of the change for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET with two gates to be next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold chatacteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering is changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.