Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Analysis of a Novel Elevated Source Drain MOSFET with Reduced Gate-Induced Drain Leakage and High Driving Capability

Gate-Induced Drain Leakage를 줄인 새로운 구조의 고성능 Elevated Source Drain MOSFET에 관한 분석

  • Kim, Gyeong-Hwan (Dept.of Electric Electronics Engineering, Yonsei University) ;
  • Choe, Chang-Sun (Dept.of Electric Electronics Engineering, Yonsei University) ;
  • Kim, Jeong-Tae (Dept.of Electric Electronics Engineering, Yonsei University) ;
  • Choe, U-Yeong (Dept.of Electric Electronics Engineering, Yonsei University)
  • 김경환 (연세대학교 전기전자공학과) ;
  • 최창순 (연세대학교 전기전자공학과) ;
  • 김정태 (연세대학교 전기전자공학과) ;
  • 최우영 (연세대학교 전기전자공학과)
  • Published : 2001.06.01
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Abstract

A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer and recessed-channel depth which are determined by dry-etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current Is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side.

GIDL(Gate-Induced Drain-Leakage)을 줄일 수 있는 새로운 구조의 ESD(Elevated Source Drain) MOSFET을 제안하고 분석하였다. 제안된 구조는 SDE(Source Drain Extension) 영역이 들려진 형태를 갖고 있어서 SDE 임플란트시 매우 낮은 에너지 이온주입으로 인한 저활성화(low-activation) 효과를 방지 할 수 있다. 제안된 구조는 건식 식각 및 LAT(Large-Angle-Tilted) 이온주입 방법을 사용하여 소오스/드레인 구조를 결정한다. 기존의 LDD MOSFET과의 비교 시뮬레이션 결과, 제안된 ESD MOSFET은 전류 구동능력은 가장 크면서 GIDL 및 DIBL(Drain Induced Barrier Lowering) 값은 효과적으로 감소시킬 수 있음을 확인하였다. GIDL 전류가 감소되는 원인으로는 최대 전계의 위치가 드레인 쪽으로 이동함에 따라 최대 밴드간 터널링이 일어나는 곳에서의 최대 전계값이 감소되기 때문이다.

Keywords

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