• 제목/요약/키워드: Cui Zhi-Yuan

검색결과 15건 처리시간 0.023초

A 10-bit Current-steering DAC in 0.35-μm CMOS Process

  • Cui, Zhi-Yuan;Piao, Hua-Lan;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • 제10권2호
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    • pp.44-48
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    • 2009
  • A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

Effect of Channel Length in LDMOSFET on the Switching Characteristic of CMOS Inverter

  • Cui, Zhi-Yuan;Kim, Nam-Soo;Lee, Hyung-Gyoo;Kim, Kyoung-Won
    • Transactions on Electrical and Electronic Materials
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    • 제8권1호
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    • pp.21-25
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    • 2007
  • A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

Electrical Characteristics of CMOS Circuit Due to Channel Region Parameters in LDMOSFET

  • Kim, Nam-Soo;Cui, Zhi-Yuan;Lee, Hyung-Gyoo;Kim, Kyoung-Won
    • Transactions on Electrical and Electronic Materials
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    • 제7권3호
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    • pp.99-102
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    • 2006
  • The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

낮은 DNL 특성을 가진 8b 2단 Folding A/D 변환기 (An 8b Two-stage Folding A/D Converter with Low DNL)

  • 최지원;도잔그엉;염창윤;이형규;김경원;김남수
    • 한국전기전자재료학회논문지
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    • 제21권5호
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    • pp.421-425
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    • 2008
  • In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

LDMOSFET에서 채널의 불순물 농도변화에 의한 CMOS회로의 전기적 특성 (Effects of Impurity Concentration in Channel of LDMOSFET on the Electrical Characteristics of CMOS Circuit)

  • 최지원;김남수;이형규
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.11-12
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    • 2005
  • 2 차원 MEDICI 시뮬레이터를 이용하여 CMOS 회로의 전기적 특성을 조사하였다. CMOS 인버터 회로는 LDMOSFET를 이용하였는데, LDMOSFET에서 전류 및 스위칭 특성에 많은 영향을 주는 곳은 채널이라고 생각되는데, 채널에서의 불순물 농도 변화에 의한 CMOS 회로의 voltage transfer특성, low input voltage($V_{IL}$), high input voltage($V_{IH}$)등을 조사하였다. LDMOSFET에서 N 채널의 농도는 $V_{IL}$에, P 채널의 농도는 $V_{IH}$에 많은 영향을 주었다.

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Expression of Tumor Necrosis Factor-alpha-induced Protein 8 in Pancreas Tissues and its Correlation with Epithelial Growth Factor Receptor Levels

  • Liu, Ke;Qin, Cheng-Kun;Wang, Zhi-Yi;Liu, Su-Xia;Cui, Xian-Ping;Zhang, Dong-Yuan
    • Asian Pacific Journal of Cancer Prevention
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    • 제13권3호
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    • pp.847-850
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    • 2012
  • Tumor necrosis factor (TNF)-alpha-induced protein 8 (TNFAIP8 or TIPE) is a recently identified protein considered to be associated with carcinogenesis. To investigate its expression pattern in pancreatic cancer patients and to analyse its correlation with clinicopathological significance and the expression levels of epithelial growth factor receptor (EGFR), immunohistochemistry was performed to detect the TNFAIP8 and EGFR proteins in pancreatic cancers, pancreatitis tissues, and healthy controls. The results showed stronger staining of TNFAIP8 protein in pancreatic cancer tissues compared with normal pancreas tissue. Furthermore, in 56 patients with pancreatic cancer, the expression levels of TNFAIP8 in patients with low tumor stage was higher than that with high tumor stage, and correlated with tumor staging and lymph node metastasis (P<0.05). Furthermore, TNFAIP8 expression positively correlated with EGFR levels (r=0.671135, P<0.05). These results indicate that TNFAIP8 may play important roles in the progression of pancreatic cancer.

수평 구조의 MOS-controlled Thyristor에서 채널에서의 길이 및 불순물 농도에 의한 스위칭 특성 (Switching Characteristics due to the Impurity Concentration and the Channel Length in Lateral MOS-controlled Thyristor)

  • 김남수;최지원;이기영;주병권;정태웅
    • 한국전기전자재료학회논문지
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    • 제18권1호
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    • pp.17-23
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    • 2005
  • The switching characteristics of MOS-Controlled Thyristor(MCT) is studied with variation of the channel length and impurity concentration in ON and OFF FET channel. The proposed MCT power device has the lateral structure and P-epitaxial layer in substrate. Two dimensional MEDICI simulator and PSPICE simulator are used to study the latch-up current and forward voltage-drop from the characteristics of I-V and the switching characteristics with variation of channel length and impurity concentration in P and N channel. The channel length and N impurity concentration of the proposed MCT power device show the strong affect on the transient characteristics of current and power. The N channel length affects only on the OFF characteristics of power and anode current, while the N doping concentration in P channel affects on the ON and OFF characteristics.

Dual Gate Emitter Switched Thyristor의 전기적 특성 (Electrical Characteristics of the Dual Gate Emitter Switched Thyristor)

  • 김남수;이응래;최지원;김영석;김경원;주변권
    • 한국전기전자재료학회논문지
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    • 제18권5호
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    • pp.401-406
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    • 2005
  • Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

Effect of MIM and n-Well Capacitors on Programming Characteristics of EEPROM

  • Lee, Chan-Soo;Cui, Zhi-Yuan;Jin, Hai-Feng;Sung, Si-Woo;Lee, Hyung-Gyoo;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • 제12권1호
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    • pp.35-39
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    • 2011
  • An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.