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http://dx.doi.org/10.4313/JKEM.2008.21.5.421

An 8b Two-stage Folding A/D Converter with Low DNL  

Cui, Zhi-Yuan (충북대학교 반도체공학과)
Cuong, Do-Danh (충북대학교 반도체공학과)
Yeom, Chang-Yoon (충북대학교 반도체공학과)
Lee, Hyung-Gyoo (충북대학교 반도체공학과)
Kim, Kyoung-Won (하이닉스 반도체 메모리연구소 분석개발팀)
Kim, Nam-Soo (충북대학교 반도체공학과)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.21, no.5, 2008 , pp. 421-425 More about this Journal
Abstract
In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.
Keywords
A/D converter; Folder; Interpolation; Comparator; CMOS process;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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