• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.853-859
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• 2014

This study presents a technique for extracting all the extrinsic parameters of HEMTs by minimizing the residual errors between a pinch-off cold-FET's gate and drain pad de-embedded Z-parameters and its modeled Z-parameters calculated by the cold-FET's remaining parameters. The presented technique allows us to successfully extract the remaining extrinsic parameter values as well as the gate and drain pad capacitance value without the additional fabrications of the gate and drain dummy pad.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.1
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• pp.109-115
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• 2000

In this paper, we propose a new method for power estimation in nodes of multi-level combinational circuits and describe its application to the extraction of common expressions for low power design. Extracting common expressions which is accomplished mostly by the extraction of kernels and common cubes, can be transformed to the problem of rectangle covering. We describe how the newly proposed estimation method can be applied to the rectangle covering problem and show the experimental results with comparisons to the results of SIS-1.2.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.21-26
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• 2004

In this paper, a direct method is developed to extact RF equivalent circuit of a packaged BJT without optimization. First, parasitic components of plastic package are removed from measured S-parameters using open and short package patterns. Using package do-embedded S-parameters, a direct and simple method is proposed to extract bonding wire inductance and chip pad capacitance between package lead and chip pad. The small-signal model parameters of internal BJT are next determined by Z and Y-parameter formula derived from RF equivalent circuit. The modeled S-parameters of packaged BJT agree well with measured ones, verifying the accuracy of this new extraction method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.118-125
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• 1999

A capacitance method to extract the metallurgical channel length of LDD MOSFET's, which is defined by the length between the metallurgical junction of substrate and source/drain under the gate, is presented. The gate capacitances of the finger type and plate type LDD MOSFET gate test patterns with same total gate area are measured. The gate bias of each pattern is changed, and the capacitances are measured with source, drain, and substrate bias grounded. The differences between two test pattern's capacitance data are plotted. The metallurgical channel length is extracted from the peak data at a maximum point using a simple formula. The numerical simulation using two-dimensional device simulator is performed to verify the proposed method.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.11
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• pp.82-88
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• 2015

In recent years, numerous studies have attempted to find and explore the auxiliary brake and the oil pressure type and electrical type are mainly used. However, the model proposed here is to self-excited eddy current brake. The advantage of this is it does not require an external power supply and can be produced to reduce the size than others. This self-eddy current brake consists of RLC circuit so resistance, inductance and capacitance value can be considered a fixed value. But, inductance and resistance value changes depending on the shape, temperature and magnetic alteration. Therefore, in this paper, the focal point is characteristic analysis according to the parameter variations. Also, using this result, this paper explains how to estimate the capacitance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.1-6
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• 2010

In this paper, RF Capacitance-Voltage(C-V) curve of short-channel MOSFET has been extracted from the room temperature to $225^{\circ}C$ using a RF method based on measured S-parameter data, and its high-temperature dependent characteristics are empirically modeled. It is observed that the voltage shift according to the variation of temperature in the weak inversion region of RF C-V curves is lower than the threshold voltage shift, but it is confirmed that this phenomenon is unexplainable with a long-channel theoretical C-V equation. The new empirical equation is developed for high-temperature dependent modeling of short-channel MOSFET C-V curves. The accuracy of this equation is demonstrated by observing good agreements between the modeled and measured C-V data in the wide range of temperature. It is also confirmed that the channel capacitance decreases with increasing temperature at high gate voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.1-9
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• 2000

A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.33-39
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• 2006

An empirical nonlinear model with intrinsic nonlinear elements has been newly developed to predict the RF nonlinear characteristics of nano-scale bulk MOSFET accurately over the wide bias range. Using an extraction method suitable for nano-scale MOSFET, the bias-dependent data of intrinsic model parameters have been accurately obtained from measured S-parameters. The intrinsic nonlinear capacitance and drain current equations have been empirically obtained through 3-dimensional curve-fitting to their bias-dependent curves. The modeled S-parameters of 60nm MOSFET have good agreements with measured ones up to 20GHz in the wide bias range, verifying the accuracy of the nano-scale MOSFET model.