• 센서학회지
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• 제28권2호
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• pp.71-75
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• 2019

This paper proposes the extension of the dynamic range in complementary metal oxide semiconductor (CMOS) image sensors (CIS) using switching operation of in-pixel inverter. A CMOS inverter is integrated in each unit pixel of the proposed CIS for switching operations. The n+/p-substrate photodiode junction capacitances are added to each unit pixel. When the output voltage of the photodiode is less than half of the power supply voltage of the CMOS inverter, the output voltage of the CMOS inverter changes from 0 V to the power supply voltage. Hence, the output voltage of the CMOS inverter is adjusted by changing the supply voltage of the CMOS inverter. Thus, the switching point is adjusted according to light intensity when the supply voltage of the CMOS inverter changes. Switching operations are then performed because the CMOS inverter is integrated with in each unit pixel. The proposed CIS is composed of a pixel array, multiplexers, shift registers, and biasing circuits. The size of the proposed pixel is $10{\mu}m{\times}10{\mu}m$. The number of pixels is $150(H){\times}220(V)$. The proposed CIS was fabricated using a $0.18{\mu}m$ 1-poly 6-metal CMOS standard process and its characteristics were experimentally analyzed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1993년도 추계학술대회 논문집
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• pp.93-96
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• 1993

BiCMOS technology, which combines CMOS and bipolar technology, offers the possibility of achieving both very high density and high performance. In this paper, the characteristics of BiCMOS and CMOS circuits, especilly the delay time is studied. BiCMOS inverter, which has high drive ability because of bipolar transistor, drives high load capacitance and has low-power characteristics because the current flows only during switching transient just like the CMOS gate. BiCMOS inverter has the less dependence on load capacitance than CMOS inverter. SPICE that has been used for electronic circuit analysis is chosen to simulate these circuits and the characteristics is discussed.

• Transactions on Electrical and Electronic Materials
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• 제8권1호
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• pp.21-25
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• 2007

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• 센서학회지
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• 제27권3호
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• pp.160-164
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• 2018

In this paper, a wide dynamic range complementary metal-oxide-semiconductor (CMOS) image sensor with the adjustable sensitivity by using cascode metal-oxide-semiconductor field-effect transistor (MOSFET) and inverter is proposed. The characteristics of the CMOS image sensor were analyzed through experimental results. The proposed active pixel sensor consists of eight transistors operated under various light intensity conditions. The cascode MOSFET is operated as the constant current source. The current generated from the cascode MOSFET varies with the light intensity. The proposed CMOS image sensor has wide dynamic range under the high illumination owing to logarithmic response to the light intensity. In the proposed active pixel sensor, a CMOS inverter is added. The role of the CMOS inverter is to determine either the conventional mode or the wide dynamic range mode. The cascode MOSFET let the current flow the current if the CMOS inverter is turned on. The number of pixels is $140(H){\times}180(V)$ and the CMOS image sensor architecture is composed of a pixel array, multiplexer (MUX), shift registers, and biasing circuits. The sensor was fabricated using $0.35{\mu}m$ 2-poly 4-metal CMOS standard process.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.407-410
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• 1987

A layout design concept which suppress the substrate current generated during the switching transients of an CMOS inverter is presented. The amount of hot carriers and the peak value of substrate current can be reduced by changing the device geometry ratio of driver and load device of an CMOS inverter.

• 전자공학회논문지D
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• 제35D권4호
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• pp.71-77
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• 1998

In this paper, algeration of electical characteristics is analyzed when the operating temperature of MOSFET, BJT and CMOS/BiCMOS inverter is lowered from 300K to 77K. As the operating temperature is lowered, electric characteristics of MOSFET are enhanced generally but, those of bipolar transistor are degraded because current gain is reduced by BGN(Band Gap Narrowing) effect. For the inverter considered in this work, switching characteristics of PSA-BiCMOS inverter are enhanced by the electrical characteristics enhancement of MOSFET when the operating temperature is reduced to 200K, while under 200K, those of PSA-BiCMOS inverter are degraded because the degradation of BJT impacts on the inverter circuit.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1057-1060
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• 1998

Power Dissipation and circuit speed become the most importance parameters in VLSI system maximum power dissipation for VLSI system design. We remodeled CMOS inverter according to the operating region, saturation region or linear regin, and calculate maximum power dissipation point of CMOS inverter. The result of proposed maximum power dissipation model compared with those from SPICE simulation which results that the proposed maximum power dissipation model has the error rate within 10% to SPICE simulation.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 2002년도 춘계학술대회 논문집
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• pp.195-199
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• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1878-1881
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• 2002

The capacitance of nonlinear component such as a CMOS inverter varies largely around the threshold voltage. We measured the far-end crosstalk of two parallel microstrip lines with the CMOS inverter load near the threshold voltage of the CMOS inverter, The negative voltage of the crosstalk agrees with that for a 4pF capacitor toad. The positive voltage of the crosstalk hardly changes of the amplitude of the input step voltage.

• Transactions on Electrical and Electronic Materials
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• 제7권3호
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• pp.99-102
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• 2006

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.