Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1987.07a
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- Pages.407-410
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- 1987
New Layout Design Concept for Suppressing the Substrate Current in CMOS Inverter
CMOS Inverter의 Substrate Current를 줄이는 Layout 설계
- Park, Heung-Joon (Dept. of Electrical Engineering, KAIST) ;
- Kim, Choong-Ki (Dept. of Electrical Engineering, KAIST)
- Published : 1987.07.03
Abstract
A layout design concept which suppress the substrate current generated during the switching transients of an CMOS inverter is presented. The amount of hot carriers and the peak value of substrate current can be reduced by changing the device geometry ratio of driver and load device of an CMOS inverter.
Keywords