• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.615-616
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• 2006

Nowadays, the need of multi-mode/multi-band transceiver is rapidly increasing, so we design a direct conversion RF front-end for multi-mode/multi-band receiver that support WCDMA/CDMA2000/WIBRO standard. It consists of variable gain reconfigurable LNA and single input double balanced Mixer and complementary differential LC Oscillator. The circuit is implemented in 0.18 um RF CMOS technology and is suitable for low-cost mode/multi-band.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.313-319
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• 2012

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-${\mu}m$ standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-${\mu}A$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• Journal of electromagnetic engineering and science
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• 제15권2호
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• pp.63-75
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• 2015

The CMOS power amplifier (PA) is a promising solution for highly-integrated transmitters in a single chip. However, the implementation of PAs using the CMOS process is a major challenge because of the inferior characteristics of CMOS devices. This paper focuses on improvements to the efficiency and linearity of CMOS PAs for modern wireless communication systems incorporating high peak-to-average ratio signals. Additionally, an envelope tracking supply modulator is applied to the CMOS PA for further performance improvement. The first approach is enhancing the efficiency by waveform engineering. In the second approach, linearization using adaptive bias circuit and harmonic control for wideband signals is performed. In the third approach, a CMOS PA with dynamic auxiliary circuits is employed in an optimized envelope tracking (ET) operation. Using the proposed techniques, a fully integrated CMOS ET PA achieves competitive performance, suitable for employment in a real system.

• 한국전자파학회논문지
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• 제19권6호
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• pp.597-602
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• 2008

본 논문은 고출력 전자파에 따른 CMOS IC 소자의 피해 효과와 회복 시간을 알아보았다. 고출력 전자파 발생 장치는 마그네트론을 사용하였고, CMOS 인버터의 오동작/부동작 판별법은 유관 식별이 가능한 LED 회로로 구성하였다. 그리고 고출력 전자파에 의해 오동작된 CMOS 인버터의 전원 전류와 회복 시간을 관찰하였다. 그 결과, 전계 강도가 약 9.9 kV/m에서의 전원 전류는 정상 전류의 2.14배가 증가하였다. 이는 래치업에 의한 CMOS 인버터가 오작동된 것을 확인할 수 있었다. 또한, COMS 인버터의 파괴는 컴포넌트, 온칩와이어, 그리고 본딩 와이어에서 다른 형태로 관찰하였다 위 실험 결과로, 전자 장비의 고출력 전자파 장해에 대한 이해를 돕는데 기초 자료로 활용될 것으로 예측된다.

• Journal of information and communication convergence engineering
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• 제14권4호
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.143-149
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• 2008

A novel compact model for a five-port transformer balun is proposed for the efficient circuit design of hybrid balun. Compared to the conventional model, the proposed model provides much faster computation time and more reasonable values for the extracted parameters. The hybrid balun, realized in $0.18\;{\mu}m$ CMOS, achieves 2.8 dB higher gain and 1.9 dB lower noise figure than its passive counterpart only at a current consumption of 0.67 mA from 1.2 V supply. By employing the hybrid balun, a differential zero-IF receiver is designed in $0.18\;{\mu}m$ CMOS for IEEE 802.15.4 ZigBee applications. It is composed of a differential cascode LNA, passive mixers, and active RC filters. Comparative investigations on the three receiver designs, each employing the hybrid balun, a simple transformer balun, and an ideal balun, clearly demonstrate the advantages of the hybrid balun in fully differential CMOS RF receivers. The simulated results of the receiver with the hybrid balun show 33 dB of conversion gain, 4.2 dB of noise figure with 20 kHz of 1/f noise corner frequency, and -17.5 dBm of IIP3 at a current consumption of 5 mA from 1.8 V supply.

• 한국산업융합학회 논문집
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• 제21권6호
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.