1 |
Mats G. Backstrom, "The threat from intentional EMI against the civil technical infrastructure", Reprint from ESW2006, 3rd European Survivability Workshop, pp. 16-19, May 2006
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2 |
M. Camp, H. Garbe, and D. Nitsch, "Influence of the technology on the destruction effects of semi-conducters by impact of EMP and UWB pulses", IEEE Trans. on EMC, vol. 1, pp. 87-92, 2002
|
3 |
J. E. Hall, J. A. Seitchik, L. A. Arledge, P. Yang, and P. K. Fung, "Analysis of latchup susceptibility in CMOS circuits", Electron Devices Meeting, 1984 International, vol. 30, pp. 292-295, 1984
|
4 |
D. Taylor, D. V. Giri, High-power Microwave Systems and Effects, Washington, D.C., Taylor & Francis, 1994
|
5 |
"JESD78 latch-up testing standard", Electronic Industry Association JEDEC standards, Arlington, VA.
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6 |
D. B. Estreich, "The physics and modeling of latch- up and CMOS integrated circuits", Stanford Electron. Labs., Stanford, CA, Tech. Rep. G201-9, Nov. 1980
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7 |
M. Camp, H. Gerth, H. Garbe, and H. Haase, "Predicting the breakdown behavior of microcontrollers under EMP/UWB impact using a statistical analysis", IEEE Trans. on Electromagnetic Compatibility, vol. 46, pp. 368-379, 2004
DOI
ScienceOn
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8 |
Mats G. Backstrom, "Susceptibility of electronic systems to high power microwaves: Summary of test experience", IEEE Transactions on Electromagnetic Compatibility, vol. 46, no. 3, Aug. 2004
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