Implementation and Measurement of Protection Circuits for Step-down DC-DC Converter Using 0.18um CMOS Process

0.18um CMOS 공정을 이용한 강압형 DC-DC 컨버터 보호회로 구현 및 측정

Abstract

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

Fig. 1 Power management IC in portable applications

Fig. 2 Simplified block diagram of the basic DC-DC step-down converter

Fig. 3 Block diagram of the proposed step-down DC-DC converter

Fig. 4 TSD Circuit

Fig. 5 UVLO Circuit

Fig. 6 OVP Circuit

Fig. 7 Step-down DC-DC converter chip

Fig. 8 Designed 1.5V Output Step-down DC-DC converter Layout

Fig. 9 Chip measurement

Fig. 10 UVLO measurement result

Fig. 11 OVP measurement result

Fig. 12 TSD measurement result

Table 1. Parameters of 0.18-um process for 3.3V PMOS/NMOS devices

Table 2. Summary of protection circuit performance of designed 1.5V output step-down converter