Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2006.10c
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- Pages.142-144
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- 2006
Implementation of Ternary Adder and Multiplier Using Current-Mode CMOS
전류모드 CMOS에 의한 3치 가산기 및 승산기의 구현
Abstract
In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under
Keywords