Low Drop-Out (LDO) Voltage Regulator with Improved Power Supply Rejection |
Jang, Ho-Joon
(Integrated Circuits Laboratory, Hanyang University)
Roh, Yong-Seong (Integrated Circuits Laboratory, Hanyang University) Moon, Young-Jin (Integrated Circuits Laboratory, Hanyang University) Park, Jeong-Pyo (Integrated Circuits Laboratory, Hanyang University) Yoo, Chang-Sik (Integrated Circuits Laboratory, Hanyang University) |
1 | "Application Note 883: Improved Power Supply Rejection for IC Linear Regulators," Maxim Integrated Products, Inc., Sunnyvale, CA, Oct. 2002 [Online]. Available: http://www.maximic.com/ appnotes.cfm/appnote_number/883, accessed on Dec. 4, 2008. |
2 | J. M. Ingino and V. R. von Kaenel, "A 4-GHz clock system for a high-performance system-on-achip design," IEEE J. Solid-State Circuits, pp. 1693-1698, Nov. 2001. |
3 | M. El-Nozahi, A. Amer, J. Torres, K. Entesari and E. Sanchez-Sinencio, "High PSR Low Drop-Out Regulator with Feed-Forward Ripple Cancellation Technique," IEEE J. Solid-State Circuits, vol. 45, pp. 565-577, Mar. 2010. DOI ScienceOn |
4 | S. K. Hoon, S. Chen, F. Maloberti, J. Chen, B. Aravind, "A Low Noise, High Power Supply Rejection Low Dropout Regulator for Wireless System-on-Chip Applications," IEEE Custom Integrated Circuits Conference, pp. 759-762, Sep. 2005. |
5 | B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, International Edition 2001. |
6 | V. Gupta, G. A. Rincon-Mora and P. Raha, "Analysis and Design of Monolithic, High PSR, Linear Regulator for SoC Applications," IEEE Intl. SoC Conf., pp. 311-315, Sep. 2004. |
7 | V. Gupta and G. A. Rincon-Mora, "A 5mA 0.6um CMOS Miller-Compensated LDO regulator with-27dB worst-case power-supply rejection using 60pF of on-chip capacitance," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 520-521, Feb. 2007. |
8 | A. J. Stratakos, S. R. Sanders, and R. W. Broderson, "A low-voltage CMOS dc-dc converter for a portable battery-operated system," in Proc. Power Electronics Specialists Conf., vol. 1, pp. 619-626, Jun. 1994. |
9 | P. Li, P. Hazucha, T. Karnik, and R. Bashirullah, "A delay locked loop synchronization scheme for high frequency multiphase hysteretic DC-DC converter," IEEE J. Solid-State Circuits, vol. 11, pp.3131-3145, Nov. 2009. |
10 | P. K. T. Mok, "Embedded Power Management Circuits," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Tutorials T1, Feb. 2007. |