• Title/Summary/Keyword: CMOS Process

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12-bit SAR A/D Converter with 6MSB sharing (상위 6비트를 공유하는 12 비트 SAR A/D 변환기)

  • Lee, Ho-Yong;Yoon, Kwang-Sub
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1012-1018
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    • 2018
  • In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

A 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS Algorithmic A/D Converter (14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS 알고리즈믹 A/D 변환기)

  • Park, Yong-Hyun;Lee, Kyung-Hoon;Choi, Hee-Cheol;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.65-73
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    • 2006
  • This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

Design of Low Power 12Bit 80MHz CMOS D/A Converter using Pseudo-Segmentation Method (슈도-세그멘테이션 기법을 이용한 저 전력 12비트 80MHz CMOS D/A 변환기 설계)

  • Joo, Chan-Yang;Kim, Soo-Jae;Lee, Sang-Min;Kang, Jin-Ku;Yoon, Kwang-Sub
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.13-20
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    • 2008
  • This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.

A 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS Pipeline ADC with Various Circuit Sharing Schemes (다양한 회로 공유기법을 사용하는 10비트 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS Pipeline ADC)

  • Yoon, Kun-Yong;Lee, Se-Won;Choi, Min-Ho;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.4
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    • pp.53-63
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    • 2009
  • This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

A 15b 50MS/s CMOS Pipeline A/D Converter Based on Digital Code-Error Calibration (디지털 코드 오차 보정 기법을 사용한 15비트 50MS/s CMOS 파이프라인 A/D 변환기)

  • Yoo, Pil-Seon;Lee, Kyung-Hoon;Yoon, Kun-Yong;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.5
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    • pp.1-11
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    • 2008
  • This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

Design of a Fully Integrated Low Power CMOS RF Tuner Chip for Band-III T-DMB/DAB Mobile TV Applications (Band-III T-DMB/DAB 모바일 TV용 저전력 CMOS RF 튜너 칩 설계)

  • Kim, Seong-Do;Oh, Seung-Hyeub
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.4
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    • pp.443-451
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    • 2010
  • This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

A 14b 100MS/s $3.4mm^2$ 145mW 0.18um CMOS Pipeline A/D Converter (14b 100MS/s $3.4mm^2$ 145mW 0.18un CMOS 파이프라인 A/D 변환기)

  • Kim Young-Ju;Park Yong-Hyun;Yoo Si-Wook;Kim Yong-Woo;Lee Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.5 s.347
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    • pp.54-63
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    • 2006
  • This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

A Fully-Integrated Low Phase Noise Multi-Band 0.13-um CMOS VCO using Automatic Level Controller and Switched LC Tank (자동 크기 조절 회로와 Switched LC tank를 이용한 집적화된 저위상 잡음 다중 대역 0.13-um CMOS 전압 제어 발진기)

  • Choi, Jae-Won;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.1
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    • pp.79-84
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    • 2007
  • In this paper, a fully-integrated low phase noise multi-band CMOS VCO using automatic level controller (ALC) and switched LC tank has been presented. The proposed VCO has been fabricated in a 0.13-um CMOS process. The switched LC tank has been designed with a pair of capacitors and two pairs of inductors switched using MOS switch. By using this structure, four band (2.986 ${\sim}$ 3.161, 3.488 ${\sim}$ 3.763, 4.736 ${\sim}$ 5.093, and 5.35 ${\sim}$ 5.887 GHz) operation is achieved in a single VCO. The VCO with 1.2 V power supply has phase noise of -118.105 dBc/Hz @ 1 MHz at 2.986 GHz and -113.777 dBc/Hz @ 1 MHz at 5.887 GHz, respectively. The reduced phase noise has been approximately -1 ${\sim}$ -3 dBc/Hz @ 1 MHz in the broadest tuning range, 2.986 ${\sim}$ 5.887 GHz. The VCO has consumed 4.2 ${\sim}$ 5.4 mW in the entire frequency band.

Effect of R-C Compensation on Switching Regulation of CMOS Low Dropout Regulator

  • Choi, Ikguen;Jeong, Hyeim;Yu, Junho;Kim, Namsoo
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.3
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    • pp.172-177
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    • 2016
  • Miller feedback compensation is introduced in a low dropout regulator (LDO) in order to obtain a capacitor-free regulator and improve the fast transient response. The conventional LDO has a limited bandwidth because of the large-size output capacitor and parasitic gate capacitance in the power MOSFET. In order to obtain a stable frequency response without the output capacitor, LDO is designed with resistor-capacitor (R-C) compensation and this is achieved with a connection between the gain-stage and the power MOS. An R-C compensator is suggested to provide a pole and zero to improve the stability. The proposed LDO is designed with the 0.35 μm CMOS process. Simulation testing shows that the phase margin in the Bode plot indicates a stable response, which is over 100o. In the load regulation, the transient time is within 55 μs when the load current changes from 0.1 to 1 mA.

A Design of 18 MHz Relaxation Oscillator with ±1 % Accuracy Based on Temperature Sensor (Temperature Sensor 기반 ±1 % 이내의 주파수 정확도를 가지는 18 MHz Relaxation Oscillator의 설계)

  • Kim, Sang Yun;Lee, Ju Ri;Lee, Dong Soo;Park, Hyung Gu;Kim, Hong Jin;Lee, Kang-Yoon
    • Journal of Korea Society of Industrial Information Systems
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    • v.18 no.5
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    • pp.39-44
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    • 2013
  • In this paper, a Relaxation Oscillator with temperature compensation using BGR and ADC is presented. The current to determine the frequency of Relaxation Oscillator can be controlled. By adjusting the current according to the temperature using the code that is output from the ADC and BGR, was to compensate the output frequency of the temperature. It is fabricated in a 0.35 ${\mu}m$ CMOS process with an active area of $240{\mu}m{\times}210{\mu}m$. Current consumption is 600 ${\mu}A$ from a 5 V and the rate of change of the output frequency with temperature shows about ${\pm}1%$.