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A 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS Algorithmic A/D Converter  

Park, Yong-Hyun (Dept. Of Electronic Engineering, Sogang University)
Lee, Kyung-Hoon (Dept. Of Electronic Engineering, Sogang University)
Choi, Hee-Cheol (Dept. Of Electronic Engineering, Sogang University)
Lee, Seung-Hoon (Dept. Of Electronic Engineering, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.12, 2006 , pp. 65-73 More about this Journal
Abstract
This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.
Keywords
ADC; CMOS;
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