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A 15b 50MS/s CMOS Pipeline A/D Converter Based on Digital Code-Error Calibration  

Yoo, Pil-Seon (Dept. of Electronic Engineering, Sogang University)
Lee, Kyung-Hoon (Dept. of Electronic Engineering, Sogang University)
Yoon, Kun-Yong (Dept. of Electronic Engineering, Sogang University)
Lee, Seung-Hoon (Dept. of Electronic Engineering, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.5, 2008 , pp. 1-11 More about this Journal
Abstract
This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.
Keywords
CMOS; ADC; pipeline; high-resolution; digital calibration;
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1 Y. Chiu, P. Gray, and B. Nikolic, 'A 1.8 V 14 b 10 MS/s pipelined ADC in 0.18 um CMOS with 99 dB SFDR,' in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 458-459
2 J. Goes, J. C. Vital, L. Alves, N. Ferreira, P. Ventura, E. Bach, J. E. Franca, and R. Koch, 'A low-power 14-b 5MS/s CMOS pipeline ADC with background analog self-calibration,' in Proc. ESSCIRC, Sep. 2000, pp. 172-175
3 S. H. Lee and B. S. Song, 'Digital-domain calibration of multistep analog-to-digital converters,' IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1679-1688, Dec. 1992   DOI   ScienceOn
4 M. J. Choe, B. S. Song, and K. Bacrania, 'A 13b 40MSample/s CMOS pipelined folding ADC with background offset trimming,' in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 36-37
5 G. C. Ahn, H. C. Choi, S. I. Lim, S. H. Lee, and C. D. Lee, 'A 12-b, 10-MHz, 250-mW CMOS A/D converter,' IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 2030-2035, Dec. 1996   DOI   ScienceOn
6 H. Van der Ploeg, M. Vertregt, and M. Lammers, 'A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications,' in Proc. ESSCIRC, Sep. 2005, pp. 161-164
7 S. Chen, K. Bacrania, and B. Song, 'A 14b 20MSample/s CMOS pipelined ADC,' in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 46-47
8 J. McNeill, M. C. W. Coln, and B. J. Larivee, 'Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC,' IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2437-2445, Dec. 2005   DOI   ScienceOn
9 H. C. Liu, Z. M. Lee, and J. T. Wu, 'A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration,' IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1047-1056, May 2005   DOI   ScienceOn
10 E. Siragusa and I. Galton, 'Gain error correction technique for pipelined analog-to-digital converters,' Electron. Lett., vol. 36, pp. 617-618, Mar. 2000   DOI   ScienceOn
11 I. Galton, 'Digital cancelation of D/A converter noise in pipelined A/D converters,' IEEE Trans. Circuits Syst. II, vol. 47, pp. 185-196, Mar. 2000   DOI   ScienceOn
12 S. T. Ryu, S. Ray, B. S. Song, G. H. Cho, and K. Bacrania, 'A 14-b linear capacitor self-trimming pipelined ADC,' IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2046-2051, Nov. 2004   DOI   ScienceOn
13 Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, 'Least mean square adaptive digital background calibration of pipelined analog- to-digital converters,' IEEE Trans. Circuits Syst. I, Fund. Theory Applicat., vol. 51, no. 1, pp. 38-46, Jan. 2004   DOI
14 S. Hisane and S. E. Sapp, 'A 16-bit, 20MSPS CMOS pipeline ADC with direct INL detection algorithm,' in Proc. CICC, Sep. 2003, pp. 417-420
15 S. U. Kwak, B. S. Song, and K. Bacrania, 'A 15-b, 5-Msample/s low-spurious CMOS ADC,' IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1866-1875, Dec. 1997   DOI   ScienceOn
16 U. Moon and B. Song, 'Background digital calibration techniques for pipelined ADCs,' IEEE Trans. Circuits Syst. II, vol. 44, pp. 102-109, Feb. 1997   DOI   ScienceOn
17 E. Siragusa and I. Galton, 'A digitally enhanced 1.8V 15b 40MS/s CMOS pipelined ADC,' in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 452-453
18 T. Shu, B. Song, and K. Bacrania, 'A 13-b, 10-Msample/s ADC digitally calibrated with oversampling delta-sigma converter,' IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 443-452, Apr. 1995   DOI   ScienceOn
19 Y. J. Cho, K. H. Lee, H. C. Choi, S. H Lee, K. H. Moon, and J. W. Kim, 'A calibration-free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS pipeline ADC with high-matching 3-D symmetric capacitors,' in Proc. CICC, Sep. 2006, pp. 485-488
20 S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, 'A 2.5V 10b 120 Msample/s CMOS pipelined ADC with high SFDR,' in Proc. CICC, May 2002, pp. 441-444
21 H. C. Liu, Z. M. Lee, and J. T. Wu, 'A 15b 20MS/s CMOS pipelined ADC with digital background calibration,' in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 454-455