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A 14b 100MS/s $3.4mm^2$ 145mW 0.18um CMOS Pipeline A/D Converter  

Kim Young-Ju (Dep. of Electronic Engineering, Sogang University)
Park Yong-Hyun (Dep. of Electronic Engineering, Sogang University)
Yoo Si-Wook (Dep. of Electronic Engineering, Sogang University)
Kim Yong-Woo (Dep. of Electronic Engineering, Sogang University)
Lee Seung-Hoon (Dep. of Electronic Engineering, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.5, 2006 , pp. 54-63 More about this Journal
Abstract
This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.
Keywords
high resolution; pipeline; CMOS; ADC; 3-D symmetric layout;
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