• Title/Summary/Keyword: Accurate circuit

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Hierarchical Timing Analysis considering Global False Path

  • Sunik Heo;Kim, Juho
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.235-237
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    • 2002
  • As the integrated circuit technology gets developed, a circuit size of more than thousands of transistors becomes normal. A hierarchical design is unavoidable due to a huge circuit size. It is important how we can consider hierarchical structure in circuit delay analysis. In this paper we present an accurate method to analyze the delay of circuit with hierarchical structure. Adding the notion of global false path to the hierarchical timing analysis performs more accurate timing analysis.

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The Role of a Wiring Model in Switching Cell Transients: the PiN Diode Turn-off Case

  • Jedidi, Atef;Garrab, Hatem;Morel, Herve;Besbes, Kamel
    • Journal of Power Electronics
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    • v.17 no.2
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    • pp.561-569
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    • 2017
  • Power converter design requires simulation accuracy. In addition to the requirement of accurate models of power semiconductor devices, this paper highlights the role of considering a very good description of the converter circuit layout for an accurate simulation of its electrical behavior. This paper considers a simple experimental circuit including one switching cell where a MOSFET transistor controls the diode under test. The turn-off transients of the diode are captured, over which the circuit wiring has a major influence. This paper investigates the necessity for accurate modeling of the experimental test circuit wiring and the MOSFET transistor. It shows that a simple wiring inductance as the circuit wiring representation is insufficient. An adequate model and identification of the model parameters are then discussed. Results are validated through experimental and simulation results.

An Accurate Gate-level Stress Estimation for NBTI

  • Han, Sangwoo;Lee, Junho;Kim, Byung-Su;Kim, Juho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.2
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    • pp.139-144
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    • 2013
  • Negative bias temperature instability (NBTI) has become a major factor determining circuit reliability. The effect of the NBTI on the circuit performance depends on the duty cycle which represents the stress and recovery conditions of each device in a circuit. In this paper, we propose an analytical model to perform more accurate duty cycle estimation at the gate-level. The proposed model allows accurate (average error rate: 3%) computation of the duty cycle without the need for expensive transistor-level simulations Furthermore, our model estimates the waveforms at each node, allowing various aging effects to be applied for a reliable gate-level circuit aging analysis framework.

Accurate Tunable-Gain 1/x Circuit Using Capacitor Charging Scheme

  • Yang, Byung-Do;Heo, Seo Weon
    • ETRI Journal
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    • v.37 no.5
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    • pp.972-978
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    • 2015
  • This paper proposes an accurate tunable-gain 1/x circuit. The output voltage of the 1/x circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of the process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/x circuit is tuned by a 10-bit digital code. The 1/x circuit was fabricated using a $0.18{\mu}m$ CMOS process. Its core area is $0.011mm^2$ ($144{\mu}m{\times}78{\mu}m$), and it consumes $278{\mu}W$ at $V_{DD}=1.8V$ and $f_{CLK}=1MHz$. Its error is within 1.7% at $V_{IN}=0.05V$ to 1 V.

Circuit Modeling of 3-D Parallel-plate Capacitors Fabricated by LTCC Process

  • Shin, Dong-Wook;Oh, Chang-Hoon;Yun, Il-Gu;Lee, Kyu-Bok;Kim, Jong-Kyu
    • Transactions on Electrical and Electronic Materials
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    • v.5 no.1
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    • pp.19-23
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    • 2004
  • A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

Current Sensing Circuit of MOSFET Switch for Boost Converter (부스터 변환기를 위한 MOSFET 스위치 전류 감지 회로)

  • Min, Jun-Sik;No, Bo-Mi;Kim, Eui-Jin;Lee, Chan-Soo;Kim, Yeong-Seuk
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.9
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    • pp.667-670
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    • 2010
  • In this paper, a high voltage current sensing circuit for boost converter is designed and verified by Cadence SPECTRE simulations. The current mirror pair, power and sensing metal-oxide semiconductor field effect transistors (MOSFETs) with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side lateral-diffused MOS transistor (LDMOST) switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35 ${\mu}m$ BCD process show that current sensing is accurate and the pulse frequency modulation (PFM) boost converter using the proposed current sensing circuit satisfies with the specifications.

Accurate modeling of small-signal equivalent circuit for heterojunction bipolar transistors (이종접합 바이폴라 트랜지스터에 관한 소신호 등가회로의 정확한 모델링)

  • 이성현
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.156-161
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    • 1996
  • Accurate equivalent circuit modeling using multi-circuit optimization has been perfomred for detemining small-signal model of AlGaAs/GaAs HBTs. Three equivalent circuits for a cutoff biasing and two active biasing at different curretns are optimized simultaneously to fit gheir S parameters under the physics-based constrain that current-dependent elements for one of active circuits are connected to those for another circit multiplied by the ratio of two currents. The cutoff mode circuit and the physical constrain give the advantage of extracting physically acceptable parameters, because the number of unknown variables. After this optimization, three ses of optimized model S-parameters agree well with their measured S-parameters from 0.045 GHz to 26.5GHz.

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Transient Magnetic Analysis of AC Servo Motor Using FEM coupled with External Circuit Equation (외부회로 방정식과 유한요소법을 이용한 AC 서보전동기의 과도자계 해석)

  • Yeon, Jae-Wook;Kim, Young-Bong;Hwang, Eun-Sik;Shin, Pan-Seok
    • Proceedings of the KIEE Conference
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    • 1995.07a
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    • pp.36-38
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    • 1995
  • AC servo motors are widely used for various mechatronic devices such as FA, OA and robot machines. To obtain more accurate simulation results, a method of analysis for AC servo motor is described using transient magnetic formulation coupled with external circuit equation of the motor. The external circuit of the motor to be analyzed is described using FLUX2D program and linked to multiple finite element regions. The simulation results show that transient magnetic analysis coupled with extenal circuit has more accurate than those results from magnetostatic.

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A New Approach for Accurate RTL Power Macro-Modeling

  • Kawauchi, Hirofumi;Taniguchi, Ittetsu;Fukui, Masahiro
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.1
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    • pp.11-19
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    • 2010
  • Register transfer level power macromodeling is well known as a promising technique for accurate and efficient power estimation. This paper proposes effective approaches based on the tablebased method for the RTL power macro-modeling. The new parameter SD, which characterizes the distribution of switching activities for each gate in the circuit, is one of the contributions. The new parameter SD has strong correlation with power consumption. We also propose an accurate table reference method considering the circuit characteristics. The table reference method is applicable for every table-based method and outputs more accurate power value. The experimental results show that the combination of the proposed methods reduces max error 30.36% in the best case, comparing conventional methods. The RMS error is also improved 1.70% in the best case.

A High-Voltage Current-Sensing Circuit for LED Driver IC (LED Driver IC를 위한 고전압 전류감지 회로 설계)

  • Min, Jun-Sik;No, Bo-Mi;Kim, Yeo-Jin;Kim, Yeong-Seuk
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.14-14
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    • 2010
  • A high voltage current sensing circuit for LED driver IC is designed and verfied by Cadence SPECTRE simulations. The current mirror pair, power and sensing MOSFETs with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side LDMOST switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35um BCD process show that current sensing is accurate with properly frequency compensated opamp.

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