[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.4313/TEEM.2004.5.1.019

Circuit Modeling of 3-D Parallel-plate Capacitors Fabricated by LTCC Process

Shin, Dong-Wook (Center for Information Technology of Yonsei University, Semiconductor Engineering Laboratory, Department of Electrical and Electronic Engineering, Yonsei University)
Oh, Chang-Hoon (Center for Information Technology of Yonsei University, Semiconductor Engineering Laboratory, Department of Electrical and Electronic Engineering, Yonsei University)
Yun, Il-Gu (Center for Information Technology of Yonsei University, Semiconductor Engineering Laboratory, Department of Electrical and Electronic Engineering, Yonsei University)
Lee, Kyu-Bok (Wireless Communication Research Center, Korea Electronics Technology Institute)
Kim, Jong-Kyu (Wireless Communication Research Center, Korea Electronics Technology Institute)

Publication Information

Transactions on Electrical and Electronic Materials / v.5, no.1, 2004 , pp. 19-23 More about this Journal

Abstract

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

Keywords

LTCC; integrated passives; capacitor model; circuit modeling;

Citations & Related Records

Reference

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