JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Accurate Gate-level Stress Estimation for NBTI

  • Han, Sangwoo (Department of Computer Science Engineering, Sogang University) ;
  • Lee, Junho (Department of Computer Science Engineering, Sogang University) ;
  • Kim, Byung-Su (Samsung Electronics Co. Ltd.) ;
  • Kim, Juho (Department of Computer Science Engineering, Sogang University)
  • Received : 2012.07.02
  • Accepted : 2012.11.20
  • Published : 2013.04.30
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Abstract

Negative bias temperature instability (NBTI) has become a major factor determining circuit reliability. The effect of the NBTI on the circuit performance depends on the duty cycle which represents the stress and recovery conditions of each device in a circuit. In this paper, we propose an analytical model to perform more accurate duty cycle estimation at the gate-level. The proposed model allows accurate (average error rate: 3%) computation of the duty cycle without the need for expensive transistor-level simulations Furthermore, our model estimates the waveforms at each node, allowing various aging effects to be applied for a reliable gate-level circuit aging analysis framework.

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References

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