• Transactions of Materials Processing
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• v.26 no.5
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• pp.306-313
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• 2017

This study investigated the microstructure, tensile strength, and high cycle fatigue properties of ADC12 aluminum alloys with different $Mg+Al_2Ca$ contents manufactured using die casting process. Microstructural observation identified the presence of ${\alpha}-Al$, eutectic Si, $Al_2Cu$, and Fe-intermetallic phases. The increase of $Mg+Al_2Ca$ content resulted in finer pore size and decreased pore distribution. Room temperature tensile strength tests were conducted at strain rate of $1{\times}10^{-3}/sec$. For 0.6%Mg ADC12, measured UTS, YS, and El were 305.2MPa, 157.0MPa, and 2.7%, respectively. For 0.8%Mg ADC12, measured UTS, YS, and El were 311.2 MPa, 159.4 MPa, and 2.4%, respectively. Therefore, 0.8% ADC12 alloy had higher strength and slightly decreased elongation compared to 0.6% Mg ADC12. High cycle fatigue tests revealed that 0.6% Mg ADC12 alloy had a fatigue limit of 150 MPa while 0.8% Mg ADC12 had a fatigue limit of 160MPa. It was confirmed that $Mg+Al_2Ca$ added ADC12 alloy achieved finer, spherical eutectic Si particles, and $Al_2Cu$ phases with greater mechanical and fatigue properties since size and distribution of pores and shrinkage cavities decreased as $Mg+Al_2Ca$ content increased.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.255-258
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• 1999

This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25${\mu}{\textrm}{m}$ parameters and occupies 1.0mm$\times$1.0mm. The power consumption is 48㎽ at 40MS/s with 2.5-V power supply. The INL is under $\pm$2.0LSB and the DNL. is under $\pm$1.0LSB by Matlab simulations.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.99-108
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• 2021

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.606-608
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• 2006

This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• Journal of IKEEE
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• v.23 no.2
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• pp.461-468
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• 2019

A continuous-time Delta-Sigma ADC has various benefits; it does not require an explicit anti-aliasing filter, and it is able to handle wider-band signals with less power consumption in comparison with a discrete-time Delta-Sigma ADC. However, it inherently needs to sample the signal with a high-speed clock, necessitating a complex decimation filter that operates at high speed in order to convert the modulator output to a low-rate high-resolution digital signals without causing aliasing. This paper proposes a continuous-time Delta-Sigma ADC architecture that employs pulse-width modulation and shows that the proposed architecture lends itself to a simpler implementation of the decimation filter using a lookup table.

• Journal of IKEEE
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• v.22 no.2
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• pp.514-517
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• 2018

In sensor systems, ADC (analog-to-digital converter) demands high resolution, low power consumption, and high signal bandwidth. Sigma-delta ADC achieves high resolution by high order structure and high over-sampling ratio, but it suffers from high power consumption and low signal bandwidth. SAR (successive-approximation-register) ADC achieves low power consumption, but there is a limitation to achieve high resolution due to process mismatch. This paper surveys architecture improvement of ADC to overcome these problems.

• Progress in Medical Physics
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• v.30 no.1
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• pp.22-31
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• 2019

Purpose: To develop a new diffusion-based functional MRI (fMRI) sequence to generate apparent diffusion coefficient (ADC) maps in single excitation and evaluate the contribution of b0 signal on neuronal changes. Materials and Methods: A diffusion-based fMRI sequence was designed with single measurement that can acquire images of three directions at a time, obtaining $b=0s/mm^2$ during the first baseline condition (b0_b), followed by 107 diffusion-weighted imaging (DWI) with $b=600s/mm^2$ during the baseline and visual stimulation conditions, and another $b=0s/mm^2$ during the last activation condition (b0_a). ADC was mapped in three different ways: 1) using b0_b (ADC_b) for all time points, 2) using b0_a (ADC_a) for all time points, and 3) using b0_b and b0_a (ADC_ba) for baseline and stimulation scans, respectively. The fMRI studies were conducted on the brains of 16 young healthy volunteers using visual stimulations in a 3T MRI system. In addition, the blood oxygen level dependent (BOLD) fMRI was also acquired to compare it with diffusion-based fMRI. A sample t-test was used to investigate the voxel-wise average between the subjects. Results: The BOLD data consisted of only activated voxels. However, ADC_ba data was observed in both deactivated and activated voxels. There were no statistically significant activated or deactivated voxels for DWI, ADC_b, and ADC_a. Conclusions: With the new sequence, neuronal activations can be mapped with visual stimulation as compared to the baseline condition in several areas in the brain. We showed that ADC should be mapped using both DWI and b0 images acquired with the same conditions.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.85-90
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• 2013

In this paper, 6bit SAR ADC tolerant to ionizing radiation is presented. Radiation tolerance is achieved by using the Dummy Gate Assisted (DGA) MOSFET which was proposed to suppress the leakage current induced by ionizing radiation and its comparing sample is designed with the conventional MOSFET. The designed ADC consists of binary capacitor DAC, dynamic latch comparator, and digital logic and was fabricated using a standard 0.35um CMOS process. Irradiation was performed by Co-60 gamma ray. After the irradiation, ADC designed with the conventional MOSFET did not operate properly. On the contrary, ADC designed with the DGA MOSFET showed a little parametric degradation of which DNL was increased from 0.7LSB to 2.0LSB and INL was increased from 1.8LSB to 3.2LSB. In spite of its parametric degradation, analog to digital conversion in the ADC with DGA MOSFET was found to be possible.