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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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12-bit 10-MS/s CMOS Pipeline Analog-to-Digital Converter

12-비트 10-MS/s CMOS 파이프라인 아날로그-디지털 변환기

  • Cho, Se-Hyeon (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology) ;
  • Jung, Ho-yong (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology) ;
  • Do, Won-Kyu (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology) ;
  • Lee, Han-Yeol (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology) ;
  • Jang, Young-Chan (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
  • Received : 2021.05.16
  • Accepted : 2021.06.22
  • Published : 2021.06.30
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Abstract

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-Vpp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

본 논문에서는 영상 처리용 12-비트의 10-MS/s 파이프라인 아날로그-디지털 변환기(ADC: analog-to-digital converter)가 제안된다. 제안된 ADC는 샘플-홀드 증폭기, 3개의 stage, 3-비트 플래시 ADC, 그리고 digital error corrector로 구성된다. 각 stage는 4-비트 flash ADC와 multiplying digital-to-analog ADC로 구성된다. 고해상도의 ADC를 위해 제안된 샘플-홀드 증폭기는 gain boosting을 이용하여 전압 이득을 증가시킨다. 제안된 파이프라인 ADC는 1.8V 공급전압을 사용하는 180nm CMOS 공정에서 설계되었고 차동 1V 전압을 가지는 1MHz 사인파 아날로그 입력신호에 대해 10.52-비트의 유효 비트를 가진다. 또한, 약 5MHz의 나이퀴스트 사인파 입력에 대해 측정된 유효비트는 10.12 비트이다.

Keywords

Acknowledgement

This research was supported by Kumoh National Institute of Technology (202001170001).

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