• ETRI Journal
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• v.31 no.2
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• Journal of Computing Science and Engineering
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• v.6 no.2
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• pp.79-88
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• 2012

Power continues to be a driving force in central processing units (CPU) design. Most of the advanced breakthroughs in power have been in a realm that is applicable to workstation CPUs. Advanced power management systems will manage temperature, dynamic voltage scaling and dynamic frequency scaling in a CPU. The use of power management systems for microcontrollers and embedded CPUs has been modest, and mostly focuses on very large scale integration (VLSI) level optimizations compared to system level optimizations. In this paper, a dynamic frequency controlling (DFC) technique is introduced, to lay the foundation of a system level power management system for commercial microcontrollers. The DFC technique allows a commercial microcontroller to have minor modifications on both the hardware and software side, to allow the clock frequency to change to save power; results in this study show a 10% savings. By adding an additional layer of software abstraction at the interrupt level, the microcontroller can operate without having knowledge of the current clock frequency, and this can be accomplished without having to use an embedded operating system.

• Journal of information and communication convergence engineering
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• v.14 no.1
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• pp.26-34
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• 2016

The alignment of DNA sequences is one of the important processes in the field of bioinformatics. The Smith-Waterman algorithm (SWA) performs optimally for aligning sequences but is computationally expensive. Field programmable gate array (FPGA) performs the best on parameters such as cost, speed-up, and ease of re-configurability to implement SWA. The performance of FPGA-based SWA is dependent on efficient cell-basic implementation-unit design. In this paper, we present an optimized systolic cell design while avoiding oversimplification, very large-scale integration (VLSI)-level design, and direct mapping of iterative equations such as previous cell designs. The proposed design makes efficient use of hardware resources and provides portability as the proposed design is not based on gate-level details. Our cell design implementing a linear gap penalty resulted in a performance improvement of 32× over a GPP platform and surpassed the hardware utilization of another implementation by a factor of 4.23.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.10a
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• pp.5-7
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• 2018

VLSI(Very large scale integration) 기술을 통한 트랜지스터의 소형화를 통해 CMOS 집적 회로의 성능은 지속적으로 발전해 왔다. 이와 같은 기술 발전에 따라 집적 회로를 구성하는 디지털 논리 요소 또한 진화를 하고 있다. 디코더는 부호화된 정보를 다시 부호화되기 전으로 되돌아가는 처리를 하는 디지털 논리 요소이며 컴퓨터 설계에서 많이 사용되는 핵심 요소이다. 본 논문에서는 양자점 셀룰라 오토마타(Quantum Cellular-Automata, QCA)를 사용하여 인에이블 입력을 가진 2-to-4 디코더를 제안하였다. 4-입력 유니버설 게이트의 하나의 입력을 1로 고정시켜 3-입력 NOR 게이트로 사용하며, 입력 값 X와 입력 값 Y의 중복된 배선 수를 감소시키고 한 배선으로 두 게이트에 입력을 연결하여 디코더의 배선 수와 배선 교차부를 최소화한다. 제안안하는 4-to-2 인에이블 디코더는 기존 디코더보다 셀의 개수와 클럭수를 감소시켜 디코더의 성능을 더 효율적으로 향상시켰다. 이를 통해 고속 회로 설계에 활용 및 높은 성능을 기대 할 수 있으며 QCA 연구에 기여할 수 있을 것으로 전망 한다.

• Journal of Semiconductor Engineering
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• v.2 no.3
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• pp.136-141
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• 2021

This paper analyzes the tree expansion for multiple-input multiple-output (MIMO) detection in the viewpoint of hardware implementation. The tree expansion is to calculate path metrics of child nodes performed in every visit to a node while traversing the detection tree. Accordingly, the tree-expansion unit (TEU), which is responsible for such a task, has been an essential component in a MIMO detector. Despite the paramount importance, the analyses on the TEUs in the literature are not thorough enough. Accordingly, we further investigate the hardware complexity of the TEUs to suggest a guideline for selection. In this paper, we focus on a pair of major ways to implement the TEU: 1) a full parallel realization; 2) a transformation of the formulae followed by common subexpression elimination (CSE). For a logical comparison, the numbers of multipliers and adders are first enumerated. To evaluate them in a more practical manner, the TEUs are implemented in a 65-nm CMOS process, and their propagation delays, gate counts, and power consumptions were measured explicitly. Considering the target specification of a MIMO system and the implementation results comprehensively, one can choose which architecture to adopt in realizing a detector.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.13-19
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• 2020

In this paper, we propose a multiplexer based scheme that performs modular AB² multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB² multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB² multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB² multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.37-43
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• 2020

In this paper, we propose an efficient AB² multiplication algorithm using SPB(shifted polynomial basis) over finite fields. Using the feature of the SPB, we split the equation for AB² multiplication into two parts. The two partitioned equations are executable at the same time, and we derive an algorithm that processes them in parallel. Then we propose an efficient semi-systolic AB² multiplier based on the proposed algorithm. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the proposed AB² multiplier saves about 94%, 87%, 86% and 83% of the AT complexity of the multipliers of Wei, Wang-Guo, Kim-Lee, Choi-Lee, respectively. Therefore, the proposed multiplier is suitable for VLSI implementation and can be easily adopted as the basic building block for various applications.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Transactions on Electrical and Electronic Materials
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• v.17 no.2
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• pp.92-97
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• 2016

This paper presents design and simulation of wide band RF microswitch that uses electrostatic actuation for its operation. RF MEMS devices exhibit superior high frequency performance in comparison to conventional devices. Similar techniques that are used in Very Large Scale Integration (VLSI) can be employed to design and fabricate MEMS devices and traditional batch-processing methods can be used for its manufacturing. The proposed switch presents a novel design approach to handle reliability concerns in MEMS switches like dielectric charging effect, micro welding and stiction. The shape has been optimized at actuation voltage of 14-16 V. The switch has an improved restoring force of 20.8 μN. The design of the proposed switch is very elemental and primarily composed of electrostatic actuator, a bridge membrane and coplanar waveguide which are suspended over the substrate. The simple design of the switch makes it easy for fabrication. Typical insertion and isolation of the switch at 1 GHz is -0.03 dB and -71 dB and at 85 GHz it is -0.24 dB and -29.8 dB respectively. The isolation remains more than - 20 db even after 120 GHz. To our knowledge this is the first demonstration of a metal contact switch that shows such a high and sustained isolation and performance at W-band frequencies with an excellent figure-of merit (fc=1/2.pi.Ron.Cu =1,900 GHz). This figure of merit is significantly greater than electronic switching devices. The switch would find extensive application in wideband operations and areas where reliability is a major concern.