ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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Test-Generation-Based Fault Detection in Analog VLSI Circuits Using Neural Networks

  • Kalpana, Palanisamy (Department of Electronics and Communication Engineering, PSG College of Technology) ;
  • Gunavathi, Kandasamy (Department of Electronics and Communication Engineering, PSG College of Technology)
  • Received : 2008.07.07
  • Accepted : 2009.01.24
  • Published : 2009.04.30
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Abstract

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

Keywords

References

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