• Title/Summary/Keyword: top and bottom gate voltage

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Characteristics of CNT Field Effect Transistor (탄소나노튜브 트랜지스터 특성 연구)

  • Park, Yong-Wook;Na, Sang-Yeob
    • The Journal of the Korea institute of electronic communication sciences
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    • v.5 no.1
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    • pp.88-92
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    • 2010
  • Bottom gate and top gate field-effect transistor based carbon nanotube(CNT) were fabricated by CMOS process. Carbon nanotube directly grown by thermal chemical vapor deposition(CVD) using Ethylene ($C_2H_4$) gas at $700^{\circ}C$. The growth properties of CNTs on the device were analyzed by SEM and AFM. The electrical transport characteristics of CNT FET were investigated by I-V measurement. Transport through the nanotubes is dominated by holes at room temperature. By varying the gate voltage, bottom gate and top gate field-effect transistor successfully modulated the conductance of FET device.

Conduction Path Dependent Threshold Voltage for the Ratio of Top and Bottom Oxide Thickness of Asymmetric Double Gate MOSFET (비대칭 이중게이트 MOSFET의 상하단 산화막 두께비에 따른 전도중심에 대한 문턱전압 의존성)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.11
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    • pp.2709-2714
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    • 2014
  • This paper has analyzed the change of threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness of asymmetric double gate MOSFET. The asymmetric double gate MOSFET has the advantage that the factor to be able to control the current in the subthreshold region increases. The analytical potential distribution is derived from Poisson's equation to analyze the threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness. The Gaussian distribution function is used as charge distribution. This analytical potential distribution is used to derive off-current and subthreshold swing. By observing the results of threshold voltage and conduction path with parameters of bottom gate voltage, channel length and thickness, projected range and standard projected deviation, the threshold voltage greatly changed for the ratio of top and bottom gate oxide thickness. The threshold voltage changed for the ratio of channel length and thickness, not the absolute values of those, and it increased when conduction path moved toward top gate. The threshold voltage and conduction path changed more greatly for projected range than standard projected deviation.

Analysis of Subthreshold Swing for Channel Length of Asymmetric Double Gate MOSFET (채널길이에 대한 비대칭 이중게이트 MOSFET의 문턱전압이하 스윙 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.2
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    • pp.401-406
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    • 2015
  • The change of subthreshold swing for channel length of asymmetric double gate(DG) MOSFET has been analyzed. The subthreshold swing is the important factor to determine digital chracteristics of transistor and is degraded with reduction of channel. The subthreshold swing for channel length of the DGMOSFET developed to solve this problem is investigated for channel thickness, oxide thickness, top and bottom gate voltage and doping concentration. Especially the subthreshold swing for asymmetric DGMOSFET to be able to be fabricated with different top and bottom gate structure is investigated in detail for bottom gate voltage and bottom oxide thickness. To obtain the analytical subthreshold swing, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. As a result, subthreshold swing is sensitively changed according to top and bottom gate voltage, channel doping concentration and channel dimension.

Electrical Properties of CuPc FET Using Two-type Electrode Structure (두 가지 타입의 CuPC FET 전극 구조에서의 전기적 특성)

  • Lee, Won-Jae;Lee, Ho-Shik
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.12
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    • pp.988-991
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    • 2011
  • We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different device structure as a bottom and top contact FET. Also, we used a $SiO_2$ as a gate insulator and analyzed using a current-voltage (I-V) characteristics of the bottom and top contact CuPc FET device. In order to discuss the channel formation, we were observed the capacitance-gate voltage(C-V) characteristics of the bottom and top contact CuPc FET device.

Threshold voltage control in dual gate ZnO-based thin film transistors

  • Park, Chan-Ho;Lee, Ki-Moon;Lee, Kwang-H.;Lee, Byoung-H.;Sung, Myung-M.;Im, Seong-Il
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.527-530
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    • 2009
  • We report on the fabrication of ZnO-based dual gate (DG) thin-film transistors (TFTs) with 20 nm-thick $Al_2O_3$ for both top and bottom dielectrics, which were deposited by atomic layer deposition on glass substrates at $200^{\circ}C$. Whether top or bottom gate is biased for sweep, our TFT almost symmetrically operates under a low voltage of 5 V showing a field mobility of ~0.4 $cm^2/V{\cdot}s$ along with the on/off ratio of $5{\times}10^4$. The threshold voltage of our DG TFT was systematically controlled from 0.5 to 2.0 V by varying counter gate input from +5 to -2 V.

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Threshold Voltage Control of Pentacene Thin-Film Transistor with Dual-Gate Structure

  • Koo, Jae-Bon;Ku, Chan-Hoe;Lim, Sang-Chul;Lee, Jung-Hun;Kim, Seong-Hyun;Lim, Jung-Wook;Yun, Sun-Jin;Yang, Yong-Suk;Suh, Kyung-Soo
    • Journal of Information Display
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    • v.7 no.3
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    • pp.27-30
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    • 2006
  • This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

Threshold Voltage control of Pentacene Thin-Film Transistor with Dual-Gate Structure

  • Koo, Jae-Bon;Ku, Chan-Hoe;Lim, Sang-Chul;Lee, Jung-Hun;Kim, Seong-Hyun;Lim, Jung-Wook;Yun, Sun-Jin;Yang, Yong-Suk;Suh, Kyung-Soo
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.1103-1106
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    • 2006
  • We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.

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Analysis of Tunneling Current for Bottom Gate Voltage of Sub-10 nm Asymmetric Double Gate MOSFET (10 nm이하 비대칭 이중게이트 MOSFET의 하단 게이트 전압에 따른 터널링 전류 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.1
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    • pp.163-168
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    • 2015
  • This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.

Dependence of Channel Doping Concentration on Drain Induced Barrier Lowering for Asymmetric Double Gate MOSFET (비대칭 이중게이트 MOSFET에 대한 DIBL의 채널도핑농도 의존성)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.4
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    • pp.805-810
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    • 2016
  • The dependence of drain induced barrier lowering(DIBL) is analyzed for doping concentration in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to top/bottom gate oxide thickness and bottom gate voltage as well as channel doping concentration. As a results, the DIBL is significantly influenced by channel doping concentration. DIBL is significantly increased by doping concentration if channel length becomes under 25 nm. The deviation of DIBL is increasing with increase of oxide thickness. Top and bottom gate oxide thicknesses have relation of an inverse proportion to sustain constant DIBL regardless channel doping concentration. We also know the deviation of DIBL for doping concentration is changed according to bottom gate voltage.

Analysis of Subthreshold Swing Mechanism by Device Parameter of Asymmetric Double Gate MOSFET (소자 파라미터에 따른 비대칭 DGMOSFET의 문턱전압이하 스윙 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.1
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    • pp.156-162
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    • 2015
  • This paper has analyzed how conduction path and electron concentration for the device parameters such as oxide thickness, channel doping, and top and bottom gate voltage influence on subthreshold swing of asymmetric double gate MOSFET. Compared with symmetric and asymmetric double gate MOSFET, asymmetric double gate MOSFET has the advantage that the factors to be able to control the short channel effects increase since top and bottom gate oxide thickness and voltages can be set differently. Therefore the conduction path and electron concentration for top and bottom gate oxide thickness and voltages are investigated, and it is found the optimum conditions that the degradation of subthreshold swing, severe short channel effects, can reduce. To obtain the analytical subthreshold swing, the analytical potential distribution is derived from Possion's equation. As a result, conduction path and electron concentration are greatly changed for device parameters, and subthreshold swing is influenced by conduction path and electron concentration of top and bottom.