• Journal of Power Electronics
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• 제19권4호
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• pp.1054-1067
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• 2019

This paper systematically investigates the influence of device parameters spread on the current distribution of paralleled silicon carbide (SiC) MOSFETs. First, a variation coefficient is introduced and used as the evaluating norm for the parameters spread. Then a sample of 30 SiC MOSFET devices from the same batch of a well-known company is selected and tested under the same conditions as those on datasheet. It is found that there is big difference among parameters spread. Furthermore, comprehensive theoretical and simulation analyses are carried out to study the sensitivity of the current imbalance to variations of the device parameters. Based on the concept of the control variable method, the influence of each device parameter on the steady-state and transient current distributions of paralleled SiC MOSFETs are verified separately by experiments. Finally, some screening suggestions of devices or chips before parallel-connection are provided in terms of different applications and different driver configurations.

• 대한전자공학회논문지SD
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• 제40권5호
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• pp.290-297
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• 2003

전자와 정공의 온도 관련 이온화 계수로부터 추출한 온도 함수의 유효 이온화 계수 및 전자 이동도를 이용하여 실리콘 전력 MOSFET의 항복 전압과 on 저항을 위한 온도 함수의 해석적 표현식을 유도하였다. 온도 함수의 해석적 항복 전압 결과를 4x10/sup 14/ cm/sup -3/, 1x10/sup 15/ cm/sup -3/, 6x10/sup 16/ cm/sup -3/의 도핑 농도에 대해 각각 실험 결과와 비교하였고, 온도 및 항복 전압 함수의 on 저항 변화도 각각 실험 결과와 비교하였다. 각농도에 따른 온도 함수의 해석적 항복 전압은 77∼300k의 온도 범위에서 실험 결과와 10% 이내의 오차로 잘 일치하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권4호
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• pp.246-248
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• 2000

Closed-form expressions for the temperature dependent breakdown voltage and the on-resistance of the Si power MOSFETs were derived by employing effective temperature dependent ionization coefficient for electrons and holes. The breakdown voltage increases by 20% and the on-resistance increases 2 times when the temperature increases from 300 K to 423 K. The analytic results normalized to the values at 300 K show good agreement with the experimental data of Motorola within 3.5% and 7% for the breakdown voltage and the on-resistance, respectively.

• ETRI Journal
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• 제27권4호
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.411-412
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• 2014

In this paper, the switching losses and performances of Silicon Carbide(SiC) and Silicon based on the MOSFETs have been compared. To do this experiment, the buck converter using both SiC and Si devices have been built and tested. As a result, it has been confirmed that the converter with SiC devices shows better efficiency and performance compared with the converter using Si devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Journal of Power Electronics
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• 제18권4호
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

• 전력전자학회논문지
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• 제24권6호
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• pp.459-462
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• 2019

This work presents methods for reducing overshoot voltages across the drain-source of silicon carbide (SiC) MOSFETs in grid-connected hybrid active neutral-point-clamped (ANPC) inverters. Compared with 3-level NPC-type inverter, the hybrid ANPC inverter can realize the high efficiency. However, SiC MOSFETs conduct its switching operation at high frequencies, which cause high overshoot voltages in such devices. These overshoot voltages should be reduced because they may damage switching devices and result in electromagnetic interference (EMI). Two major strategies are used to reduce the overshoot voltages, namely, adjusting the gate resistor and using a snubber capacitor. In this paper, advantages and disadvantages of these methods will be discussed. The effectiveness of these strategies is verified by experimental results.

• Transactions on Electrical and Electronic Materials
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• 제8권3호
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• pp.110-114
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• 2007

Dependence of the thermal stability of nickel silicide on the film stress of inter layer dielectric (ILD) layer has been investigated in this study and silicon nitride $(Si_3N_4)$ layer is used as an ILD layer. Nickel silicide was formed with a one-step rapid thermal process at $500^{\circ}C$ for 30 sec. $2000{\AA}$ thick $Si_3N_4$ layer was deposited using plasma enhanced chemical vapor deposition after the formation of Ni silicide and its stress was split from compressive stress to tensile stress by controlling the power of power sources. Stress level of each stress type was also split for thorough analysis. It is found that the thermal stability of nickel silicide strongly depends on the stress type as well as the stress level induced by the $Si_3N_4$ layer. In the case of high compressive stress, silicide agglomeration and its phase transformation from the low-resistivity nickel mono-silicide to the high-resistivity nickel di-silicide are retarded, and hence the thermal stability is obviously improved a lot. However, in the case of high tensile stress, the thermal stability shows the worst case among the stressed cases.